参数资料
型号: S29CL032J0RQAI033
厂商: SPANSION LLC
元件分类: PROM
英文描述: 1M X 32 FLASH 3.3V PROM, 48 ns, PQFP80
封装: PLASTIC, MO-108CB-1, QFP-80
文件页数: 79/79页
文件大小: 2994K
代理商: S29CL032J0RQAI033
March 30, 2009 S29CD-J_CL-J_00_B3
S29CD-J & S29CL-J Flash Family
9
Data
She e t
2.
Input/Output Descriptions and Logic Symbols
Table identifies the input and output package connections provided on the device.
Symbol
Type
Description
A19-A0
Input
Address lines for S29CD-J and S29CL-J (A18-A0 for 16Mb and A19-A0 for 32Mb).
A9 supports 12V autoselect input.
DQ31-DQ0
I/O
Data input/output
CE#
Input
Chip Enable. This signal is asynchronous relative to CLK for the burst mode.
OE#
Input
Output Enable. This signal is asynchronous relative to CLK for the burst mode.
WE#
Input
Write Enable
VCC
Supply
Device Power Supply. This signal is asynchronous relative to CLK for the burst mode.
VIO
Supply
VersatileI/OTM Input.
VSS
Supply
Ground
NC
No Connect
Not connected internally
RY/BY#
Output
Ready/Busy output and open drain which require a external pull up resistor.
When RY/BY# = VOH, the device is ready to accept read operations and commands.
When RY/BY# = VOL, the device is either executing an embedded algorithm or the
device is executing a hardware reset operation.
CLK
Input
Clock Input that can be tied to the system or microprocessor clock and provides the
fundamental timing and internal operating frequency.
ADV#
Input
Load Burst Address input. Indicates that the valid address is present on the address
inputs.
IND#
Output
End of burst indicator for finite bursts only. IND is low when the last word in the burst
sequence is at the data outputs.
WAIT#
Output
Provides data valid feedback only when the burst length is set to continuous.
WP#
Input
Write Protect Input. At VIL, disables program and erase functions in two outermost
sectors of the large bank.
ACC
Input
Acceleration input. At VHH, accelerates erasing and programming. When not used for
acceleration, ACC = VSS or VCC.
RESET#
Input
Hardware Reset.
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