- 您现在的位置：买卖IC网 > PDF目录11830 > SC16C850IET,157 (NXP Semiconductors)IC UART SINGLE W/FIFO 36-TFBGA PDF资料下载
参数资料
| 型号： | SC16C850IET,157 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 22/55页 |
| 文件大小： | 0K |
| 描述： | IC UART SINGLE W/FIFO 36-TFBGA |
| 标准包装： | 2,450 |
| 特点： | 可编程 |
| 通道数： | 1，UART |
| FIFO's： | 128 字节 |
| 规程： | RS485 |
| 电源电压： | 2.5 V ~ 3.3 V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-TFBGA |
| 供应商设备封装： | 36-TFBGA（3.5x3.5） |
| 包装： | 托盘 |
| 其它名称： | 935284685157 SC16C850IET SC16C850IET-ND |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页当前第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页
SC16C850
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 11 November 2010
29 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
7.7 Line Status Register (LSR)
This register provides the status of data transfers between the SC16C850 and the CPU.
Table 20.
Line Status Register bits description
Bit
Symbol
Description
7
LSR[7]
FIFO data error.
logic 0 = no error (normal default condition)
logic 1 = at least one parity error, framing error or break indication is in the
current FIFO data. This bit is cleared when there are no remaining error flags
associated with the remaining data in the FIFO.
6
LSR[6]
THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a
logic 1 whenever the transmit holding register and the transmit shift register are
both empty. It is reset to logic 0 whenever either the THR or TSR contains a data
character. In the FIFO mode, this bit is set to ‘1’ whenever the transmit FIFO and
transmit shift register are both empty.
5
LSR[5]
THR empty. This bit is the Transmit Holding Register Empty indicator. This bit
indicates that the UART is ready to accept a new character for transmission. In
addition, this bit causes the UART to issue an interrupt to CPU when the THR
interrupt enable is set. The THR bit is set to a logic 1 when a character is
transferred from the transmit holding register into the transmitter shift register.
The bit is reset to a logic 0 concurrently with the loading of the transmitter
holding register by the CPU. In the FIFO mode, this bit is set when the transmit
FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO.
4
LSR[4]
Break interrupt.
logic 0 = no break condition (normal default condition)
logic 1 = the receiver received a break signal (RX was a logic 0 for one
character frame time). In the FIFO mode, only one break character is loaded
into the FIFO.
3
LSR[3]
Framing error.
logic 0 = no framing error (normal default condition)
logic 1 = framing error. The receive character did not have a valid stop bit(s).
In the FIFO mode, this error is associated with the character at the top of the
FIFO.
2LSR[2]
Parity error.
logic 0 = no parity error (normal default condition)
logic 1 = parity error. The receive character does not have correct parity
information and is suspect. In the FIFO mode, this error is associated with the
character at the top of the FIFO.
1
LSR[1]
Overrun error.
logic 0 = no overrun error (normal default condition)
logic 1 = overrun error. A data overrun error occurred in the Receive Shift
Register. This happens when additional data arrives while the FIFO is full. In
this case, the previous data in the shift register is overwritten. Note that under
this condition, the data byte in the Receive Shift Register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error.
0
LSR[0]
Receive data ready.
logic 0 = no data in Receive Holding Register or FIFO (normal default
condition)
logic 1 = data has been received and is saved in the Receive Holding Register
or FIFO
相关PDF资料 |
PDF描述 |
|---|---|
| SC16IS750IBS,128 | IC UART I2C/SPI 24-HVQFN |
| SC16IS741IPW,128 | IC UART 16TSSOP |
| SC16IS740IPW,128 | IC UART SINGLE W/FIFO 16-TSSOP |
| SC16IS750IBS,157 | IC UART 64BYTE 24HVQFN |
| SC16C550BIBS,157 | IC UART SOT617-1 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SC16C850IET-G | 功能描述:UART 接口集成电路 16C 2.5-5V 5MBPS UART 128BFIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SC16C850IET-S | 功能描述:UART 接口集成电路 16C 2.5-5V 5MBPS UART 128BFIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SC16C850L | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:1.8 V single UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode parallel bus interface |
| SC16C850LIB,128 | 制造商:NXP Semiconductors 功能描述: |
| SC16C850LIB,151 | 制造商:NXP Semiconductors 功能描述: |
发布紧急采购，3分钟左右您将得到回复。