参数资料
型号: SC16C850IET,157
厂商: NXP Semiconductors
文件页数: 24/55页
文件大小: 0K
描述: IC UART SINGLE W/FIFO 36-TFBGA
标准包装: 2,450
特点: 可编程
通道数: 1,UART
FIFO's: 128 字节
规程: RS485
电源电压: 2.5 V ~ 3.3 V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 36-TFBGA
供应商设备封装: 36-TFBGA(3.5x3.5)
包装: 托盘
其它名称: 935284685157
SC16C850IET
SC16C850IET-ND
SC16C850
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 11 November 2010
30 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
7.8 Modem Status Register (MSR)
This register shares the same address as EFCR register. This is a read-only register and
it provides the current state of the control interface signals from the modem, or other
peripheral device to which the SC16C850 is connected. Four bits of this register are used
to indicate the changed information. These bits are set to a logic 1 whenever a control
input from the modem changes state. These bits are set to a logic 0 whenever the CPU
reads this register.
When write, the data will be written to EFCR register.
[1]
Whenever any MSR bit 3:0 is set to logic 1, a Modem Status Interrupt will be generated.
Table 21.
Modem Status Register bits description
Bit
Symbol
Description
7
MSR[7]
CD. During normal operation, this bit is the complement of the CD input.
Reading this bit in the loopback mode produces the state of MCR[3] (OP2).
6
MSR[6]
RI. During normal operation, this bit is the complement of the RI input.
Reading this bit in the loopback mode produces the state of MCR[2] (OP1).
5
MSR[5]
DSR. During normal operation, this bit is the complement of the DSR input.
During the loopback mode, this bit is equivalent to MCR[0] (DTR).
4
MSR[4]
CTS. During normal operation, this bit is the complement of the CTS input.
During the loopback mode, this bit is equivalent to MCR[1] (RTS).
3MSR[3]
ΔCD [1]
logic 0 = no CD change (normal default condition)
logic 1 = the CD input to the SC16C850 has changed state since the last
time it was read. A modem Status Interrupt will be generated.
2MSR[2]
ΔRI [1]
logic 0 = no RI change (normal default condition)
logic 1 = the RI input to the SC16C850 has changed from a logic 0 to a
logic 1. A modem Status Interrupt will be generated.
1MSR[1]
ΔDSR [1]
logic 0 = no DSR change (normal default condition)
logic 1 = the DSR input to the SC16C850 has changed state since the
last time it was read. A modem Status Interrupt will be generated.
0MSR[0]
ΔCTS [1]
logic 0 = no CTS change (normal default condition)
logic 1 = the CTS input to the SC16C850 has changed state since the last
time it was read. A modem Status Interrupt will be generated.
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