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| 型号： | SI3225DC0-EVB |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 106/112页 |
| 文件大小： | 0K |
| 描述： | DAUGHTER CARD W/SI3200 INTERFACE |
| 标准包装： | 1 |
| 系列： | ProSLIC® |
| 主要目的： | 接口，模拟前端（AFE） |
| 已用 IC / 零件： | Si3225 |
| 已供物品： | 板，CD |
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Si3220/25 Si3200/02
Rev. 1.3
93
Not
Recommended
fo
r N
ew
D
esi
gn
s
monitor channel section. This section defines the
functionality of the six C/I bits whether they are being
transmitted to the GCI bus via the DTX pin (upstream)
or received from the GCI bus via the DRX pin
(downstream). The structure of the SC channel is
shown in Figure 62.
Figure 62. SC Channel Structure
3.31.9. Downstream (Receive) SC Channel Byte
The first six bits in the downstream SC channel control
both channels of the Dual ProSLIC where the C/I bits
are defined as follows:
Figure 63 illustrates the transmission protocol for the C/I
bits within the downstream SC channel. New data
received by either channel must be present and match
for two consecutive frames to be considered valid.
When a new command is communicated via the
downstream C/I bits, this data must be sent for at least
two consecutive frames to be recognized by the Dual
ProSLIC.
The current state of the C/I bits is stored in a primary
register, P. If the received C/I bits are identical to the
current state, no action is taken. If the received C/I bits
differ from those in register P, the new set of C/I bits is
loaded into secondary register S, and a latch is set.
When the next set of C/I bits is received during the
frame that immediately follows, the following rules
apply:
If the received C/I bits are identical to the contents of
register S, the stored C/I bits are loaded into register
P, and a valid C/I bit transition is recognized. The
latch is reset, and the Dual ProSLIC responds
accordingly to the command represented by the new
C/I bits.
If the received C/I bits differ from both the contents of
register S and the contents of register P, the newly-
received C/I bits are loaded into register S, and the
latch remains set. This cycle continues as long as
any new set of C/I bits differs from the contents of
registers S and P.
If the newly-received C/I bits are identical to the
contents of register P, the contents of register P
remain unchanged, and the latch is reset.
MSB
LSB
76
543
2
1
0
CI2A
CI1A
CI0A
CI2B
CI1B
CI0B
MR
MX
CI2A, CI1A, CI0A
Used to select operating mode for
channel A
CI2B, CI1B, CI0B
Used to select operating mode for
channel B
MR, MX
Monitor channel handshake bits
Table 49. Programming Operating Modes Using
Downstream SC Channel C/I Bits
Channel Specific C/I bits
Dual ProSLIC Operating
Mode
CI2x
CI1x
CI0x
0
Open (high impedence,
no line monitoring)
0
1
Forward Active
0
1
0
Forward On-Hook Trans-
mission
0
1
Ground Start (Tip Open)
100
Ringing
1
0
1
Reverse Active
1
0
Reverse On-Hook Trans-
mission
1
Ground Start (Ring
Open)
Note:
x = A or B, corresponding to Channel A or
Channel B.
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