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参数资料
型号： SI3225DC0-EVB
厂商： Silicon Laboratories Inc
文件页数： 65/112页
文件大小： 0K
描述： DAUGHTER CARD W/SI3200 INTERFACE
标准包装： 1
系列： ProSLIC®
主要目的： 接口，模拟前端（AFE）
已用 IC / 零件： Si3225
已供物品： 板，CD
Si3220/25 Si3200/02
56
Rev. 1.3
Not
Recommended
fo
r N
ew
D
esi
gn
s
3.15.3. Loop Closure Mask
The Dual ProSLIC implements a loop closure mask to
ensure mode change between ringing and active or on-
hook transmission without causing an erroneous loop
closure detection. The loop closure mask register,
LCRMASK, should be set such that loop closure
detection is ignored for the time (LCRMASK 1.25 ms/
LSB). The programmed time is set to mask detection of
transitional currents that occur when exiting the ringing
mode while driving a reactive load (i.e., 5 REN). A
typical setting is 80 ms (LCRMASK = 0x40).
3.15.4. Si3220 Ring Trip Detection
The Si3220 provides the ability to process a ring trip
event using an ac-based detection scheme. Using this
scheme eliminates the need to add dc offset to the
ringing signal, which reduces the total power dissipation
during the ringing state and maximizes the available
ringing amplitude. This scheme is valid for shorter loop
lengths only since it cannot reliably detect a ring trip
event if the off-hook line impedance overlaps the on-
hook impedance at 20 Hz.
Table 30. Recommended Values for Ring Trip Registers and RAM Addresses1
Ringing
Method
Ringing
Frequency
DC
Offset
Added?
RTPER
RTACTH
RTDCTH
RTACDB/
RTDCDB
Internal
(Si3220)
16–32 Hz
Yes
800/fRING
221 x RTPER
0.577(RTPER x VOFF)
See Note 2
No
800/fRING
1.59 x VRING,PK x RTPER
32767
33–60 Hz
Yes
2(800/
fRING)
221 x RTPER
0.577(RTPER x VOFF)
No
2(800/
fRING)
1.59 x VRING,PK x RTPER
32767
External
(Si3225)
16–32 Hz
Yes
800/fRING
32767
0.067 xRTPER xVOFF
33–60 Hz
Yes
2(800/
fRING)
32767
0.067 xRTPER xVOFF
Notes:
1. All calculated values should be rounded to the nearest integer.
2. Refer to Ring Trip Debounce Interval for RTACDB and RTDCDB equations.
Table 31. Register and RAM Locations Used for Ring Trip Detection
Parameter
Register/RAM
Mnemonic
Register/RAM
Bits
Programmable
Range
Resolution
Ring Trip Interrupt Pending
IRQVEC2
RTRIPS
Yes/No
N/A
Ring Trip Interrupt Enable
IRQEN2
RTRIPE
Enabled/Disabled
N/A
AC Ring Trip Threshold
RTACTH
RTACTH[15:0]
See Table 30
DC Ring Trip Threshold
RTDCTA
RTDCTH[15:0]
See Table 30
Ring Trip Sample Period
RTPER
RTPER[15:0]
See Table 30
Linefeed Shadow (monitor only)
LINEFEED
LFS[2:0]
N/A
Ring Trip Detect Status
(monitor only)
LCRRTP
RTP
N/A
AC Ring Trip Detect Debounce
Interval
RTACDB
RTACDB[15:0]
0 to 40.96 s
1.25 ms
DC Ring Trip Detect Debounce
Interval
RTDCDB
RTDCDB[15:0]
0 to 40.96 s
1.25 ms
Loop Current Sense
(monitor only)
ILOOP
ILOOP[15:0]
0 to 101.09 mA
See
Table 21
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