- 您现在的位置：买卖IC网 > PDF目录16215 > SI3225DC0-EVB (Silicon Laboratories Inc)DAUGHTER CARD W/SI3200 INTERFACE PDF资料下载
参数资料
| 型号： | SI3225DC0-EVB |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 72/112页 |
| 文件大小： | 0K |
| 描述： | DAUGHTER CARD W/SI3200 INTERFACE |
| 标准包装： | 1 |
| 系列： | ProSLIC® |
| 主要目的： | 接口，模拟前端（AFE） |
| 已用 IC / 零件： | Si3225 |
| 已供物品： | 板，CD |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页当前第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页
Si3220/25 Si3200/02
62
Rev. 1.3
Not
Recommended
fo
r N
ew
D
esi
gn
s
3.18. Two-Wire Impedance Synthesis
Two-wire impedance synthesis is performed on-chip to
optimally match the output impedance of the Dual
ProSLIC to the impedance of the subscriber loop thus
minimizing the receive path signal reflected back onto
the transmit path. The Dual ProSLIC chipset provides
on-chip, digitally-programmable, two-wire impedance
synthesis to meet return loss requirements against
virtually any global two-wire impedance requirement.
Real and complex two-wire impedances are realized by
a programmable digital filter block. (See ZA and ZD
blocks in Figure 11 on page 25.)
Figure 33. Two-Wire Impedance Synthesis
Configuration
The two-wire impedance is programmed by loading the
desired real or complex impedance value into the
Si322X coefficient generator software in the format RS +
the appropriate hex coefficients and loads them into the
appropriate control registers (registers 33–52). The two-
wire impedance can be set to any real or complex value
within the boundaries set in Table 34. The actual
impedance presented to the subscriber loop varies with
series impedance from protection devices placed
between the Dual ProSLIC chipset outputs and the TIP/
RING pair according to the following equation:
Where:
ZT is the termination impedance presented to the
TIP/RING pair
RPROT is the series resistance caused by protection
devices
RS is the series portion of the synthesized
impedance
RP||CP is the parallel portion of the synthesized
impedance
The user must enter the value of RPROT into the
software so the equalizer block can compensate for
additional series impedance. (See Figure 11 on page
illustrates
the
simplified
two-wire
impedance
circuit
including
external
protection
resistors, where ZL is the actual line impedance for the
specific geographical region. The Dual ProSLIC devices
can accomodate up to 50
of series protection
impedance per leg.
The ac impedance generation scheme is comprised of
analog and DSP-based coefficients. To turn off the
analog coefficients (RS, ZP, and ZZ bits in the ZRS and
ZZ registers), the user can simply set the ZSDIS bit of
the ZZ register to 0. To turn off the DSP coefficients
(ZA1H1 through ZB3LO registers), each register must
be loaded with 0x00.
Figure 34. Two-Wire Impedance Simplified
Circuit
3.18.1. Impedance Synthesis Initialization
and Control
The Si322x utilizes a digital IIR filter to implement SLIC
impedance synthesis. Under normal operation, the
Si322x state machine controls the clocks to this filter
automatically such that the filter clocks are turned OFF
during those times when the filter is not required. During
pulse dialing, for example, the clocks are shut OFF
during the break period and turned back ON during the
make period.
When the clocks are shut OFF, the IIR filter holds the
last sample values in its storage elements. When the
Table 34. Two-Wire Impedance
Synthesis Limitations
Desired
Configuration
Programmable Limits
RS only
100–1000
RS + CP
RS x CP > 0.5 ms
RS + RP||CP
RS/(RS + RP) > 0.1
R
P
C
P
R
S
Z
T
2R
PROT
R
S
R
P
C
P
+
+
=
Dual
ProSLIC
Z
T
Z
L
R
PROT
R
PROT
S
i32
00
/2
TIP
RING
相关PDF资料 |
PDF描述 |
|---|---|
| SEK220M400ST | CAP ALUM 22UF 400V 20% RADIAL |
| CP2201EK | KIT EVAL FOR CP2201 ETH CTRLR |
| PM1210-820J-RC | INDUCTOR 82UH 5% 1210 SMD |
| H3WWH-6036G | IDC CABLE - HPL60H/AE60G/HPL60H |
| UPS2C471MRD | CAP ALUM 470UF 160V 20% RADIAL |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SI3225DCX-EVB | 功能描述:子卡和OEM板 Si3225 Daughter Card RoHS:否 制造商:BeagleBoard by CircuitCo 产品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| Si3225-FQ | 功能描述:电信线路管理 IC Dual-Channel SLIC/ codec RoHS:否 制造商:STMicroelectronics 产品:PHY 接口类型:UART 电源电压-最大:18 V 电源电压-最小:8 V 电源电流:30 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:VFQFPN-48 封装:Tray |
| SI3225-FQR | 制造商:Silicon Laboratories Inc 功能描述: |
| Si3225-G-FQ | 功能描述:电信线路管理 IC Dual-Channel SLIC codec RoHS:否 制造商:STMicroelectronics 产品:PHY 接口类型:UART 电源电压-最大:18 V 电源电压-最小:8 V 电源电流:30 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:VFQFPN-48 封装:Tray |
| SI3225-G-FQR | 功能描述:电信线路管理 IC Dual-CH SLIC/codec Ext Ringing Support RoHS:否 制造商:STMicroelectronics 产品:PHY 接口类型:UART 电源电压-最大:18 V 电源电压-最小:8 V 电源电流:30 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:VFQFPN-48 封装:Tray |
发布紧急采购，3分钟左右您将得到回复。