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参数资料
| 型号： | SN74V263-10GGM |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| 中文描述： | 8192】18，16384】18，32768】18，65536】18的3.3V的CMOS先入先出存储器 |
| 文件页数： | 24/52页 |
| 文件大小： | 762K |
| 代理商： | SN74V263-10GGM |
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SN74V263, SN74V273, SN74V283, SN74V293
8192
×
18, 16384
×
18, 32768
×
18, 65536
×
18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D
–
JUNE 2001
–
REVISED FEBRUARY 2003
24
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
serial programming mode
If the serial programming mode has been selected as described previously, programming of PAE and PAF
values can be achieved by using a combination of the LD, SEN, WCLK, and SI inputs. Programming PAE and
PAF proceeds as follows; when LD and SEN are set low, data on the SI input are written, one bit for each WCLK
rising edge, starting with the empty offset LSB and ending with the full offset MSB. If
×
9 to
×
9 mode is selected,
a total of 28 bits for the SN74V263, 30 bits for the SN74V273, 32 bits for the SN74V283, and 34 bits for the
SN74V293. For any other mode of operation (including
×
18 bus width on either the input or output), minus 2 bits
from the previous values. So, a total of 26 bits for the SN74V263, 28 bits for the SN74V273, 30 bits for the
SN74V283, and 32 bits for the SN74V293.
See Figure 15 for timing information.
Using the serial method, individual registers cannot be programmed selectively. PAE and PAF can show a valid
status only after the complete set of bits for all offset registers has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered. When LD is low and SEN is high, no
serial write to the registers can occur.
Write operations to the FIFO are allowed before and during the serial programming sequence. In this case, the
programming of all offset bits does not have to occur at once. A select number of bits can be written to the SI
input and then, by bringing LD and SEN high, data can be written to FIFO memory via Dn by toggling WEN.
When WEN is brought high with LD and SEN restored to a low, the next offset bit in sequence is written to the
registers via SI. If an interruption of serial programming is desired, it is sufficient either to set LD low and
deactivate SEN or to set SEN low and deactivate LD. Once LD and SEN are restored to a low level, serial offset
programming continues.
From the time serial programming has begun, neither programmable flag is valid until the full set of bits required
to fill all the offset registers is written. Measuring from the rising WCLK edge that achieves the previous criteria,
PAF is valid after two more rising WCLK edges + t
PAF
, PAE is valid after the next two rising
RCLK edges + t
PAE
+ t
sk2
in synchronous timing mode.
It is not possible to read the flag offset values in a serial mode.
parallel programming mode
If the parallel programming mode has been selected as described previously, programming of PAE and PAF
values can be achieved by using a combination of the LD, WCLK , WEN and Dn inputs. If the FIFO is configured
for an input bus width and output bus width both set to
×
9, the total number of write operations required to
program the offset registers is four for the SN74V263, SN74V273, and SN74V283, or six for the SN74V293.
Refer to Figure 3 for a diagram of the data input lines D0
–
Dn used during parallel programming. If the FIFO is
configured for an input-to-output bus width of
×
9 to
×
18,
×
18 to
×
9, or
×
18 to
×
18, the following number of write
operations are required. For an input bus width of
×
18, a total of two write operations is required to program the
offset registers for the SN74V263, SN74V273, SN74V283, and SN74V293. For an input bus width of
×
9, a total
of four write operations is required to program the offset registers for the SN74V263, SN74V273, SN74V283,
and SN74V283 (see Figure 3).
For example, programming PAE and PAF on the SN74V293 configured for
×
18 bus width proceeds as follows:
when LD and WEN are set low, data on inputs Dn are written into the LSB of the empty offset register on the
first low-to-high transition of WCLK. On the second low-to-high transition of WCLK, data are written into the MSB
of the empty offset register. On the third low-to-high transition of WCLK, data are written into the LSB of the full
offset register. On the fourth low-to-high transition of WCLK, data are written into the MSB of the full offset
register. On the fifth low-to-high transition of WCLK, data are written again to the empty offset register. Note that,
for
×
9 bus width, one additional write cycle is required for the empty offset register and full offset register.
See Figure 16 for timing information.
相关PDF资料 |
PDF描述 |
|---|---|
| SN74V263-15GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V263-7GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V273-10GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V273-15GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V273-6GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SN74V263-10PZA | 功能描述:先进先出 8192 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V263-15GGM | 功能描述:先进先出 8192 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V263-15PZA | 功能描述:先进先出 8192 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V263-6GGM | 功能描述:先进先出 8192 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V263-6PZA | 功能描述:先进先出 8192 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
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