SN74V263-10GGM PDF资料下载(46/52 页)8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIR

您好，
买卖IC网欢迎您。
请登录
免费注册

您现在的位置：买卖IC网 > PDF目录374873 > SN74V263-10GGM (Texas Instruments, Inc.) 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES PDF资料下载

参数资料

型号：	SN74V263-10GGM
厂商：	Texas Instruments, Inc.
英文描述：	8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
中文描述：	8192】18，16384】18，32768】18，65536】18的3.3V的CMOS先入先出存储器
文件页数：	46/52页
文件大小：	762K
代理商：	SN74V263-10GGM

SN74V263, SN74V273, SN74V283, SN74V293

8192

18, 16384

18, 32768

18, 65536

3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

SCAS669D

–

JUNE 2001

–

REVISED FEBRUARY 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

depth-expansion configuration (FWFT mode only)

The SN74V263 can be adapted easily to applications requiring depths greater than 8192 when the

18 input

18 output bus width is selected, 16384 for the SN74V273, 32768 for the SN74V283, and 65536 for the

SN74V293. When both

9 input and

9 output bus widths are selected, depths greater than 16384 can be

adapted for the SN74V263, 32768 for the SN74V273, 65536 for the SN74V283, and 131072 for the SN74V293.

In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs

of the next), with no external logic necessary. The resulting configuration provides a total depth equivalent to

the sum of the dpths associated with each single FIFO. Figure 24 shows a depth expansion using two

SN74V263, SN74V273, SN74V283, and SN74V293 devices.

Care should be taken to select FWFT mode during master reset for all FIFOs in the depth-expansion

configuration. The first word written to an empty configuration passes from one FIFO to the next (ripple down)

until it finally appears at the outputs of the last FIFO in the chain. No read operation is necessary, but the RCLK

of each FIFO must be free running. Each time the data word appears at the outputs of one FIFO, that device

’

OR line goes low, enabling a write to the next FIFO in line.

REN

Data In

Write Enable

Write Clock

SN74V263

SN74V273

SN74V283

SN74V293

FWFT/SI

Transfer Clock

WCLK

WEN

RCLK

REN

WCLK

WEN

RCLK

Read Clock

Read Enable

Input Ready

Output Ready

Output Enable

Data Out

GND

SN74V263

SN74V273

SN74V283

SN74V293

FWFT/SI

Figure 24. Depth-Expansion Block Diagram

(For the

18 Input or

18 Output Bus Width: 16384

18, 32768

18, 65536

18, and 131072

18)

(For Both

9 Input and

9 Output Bus Width: 32768

9, 65536

9, 131072

9, and 262144

For an empty expansion configuration, the amount of time it takes for OR of the last FIFO in the chain to go low

(i.e., valid data to appear on the last FIFO

’

s outputs) after a word has been written to the first FIFO is the sum

of the delays for each FIFO:

–

transfer clock) + 3

RCLK

where N is the number of FIFOs in the expansion and T

RCLK

is the RCLK period. Note that extra cycles should

be added for the possibility that the t

sk1

specification is not met between WCLK and transfer clock, or RCLK and

transfer clock, for the OR flag.

The ripple-down delay is noticeable only for the first word written to an empty depth-expansion configuration.

There is no delay evident for subsequent words written to the configuration.

The first free location created by reading from a full-depth-expansion configuration bubbles up from the last

FIFO to the previous one until it finally moves into the first FIFO of the chain. Each time a free location is created

in one FIFO of the chain, that FIFO

’

s IR line goes low, enabling the preceding FIFO to write a word to fill it.

For a full-expansion configuration, the amount of time it takes for IR of the first FIFO in the chain to go low after

a word has been read from the last FIFO is the sum of the delays for each individual FIFO:

–

transfer clock) + 2T

WCLK

where N is the number of FIFOs in the expansion and T

WCLK

is the WCLK period. Note that additional cycles

should be added for the possibility that the t

sk1

specification is not met between RCLK and transfer clock, or

WCLK and transfer clock, for the IR flag.

相关PDF资料	PDF描述
SN74V263-15GGM	8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SN74V263-7GGM	8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SN74V273-10GGM	8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SN74V273-15GGM	8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SN74V273-6GGM	8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

相关代理商/技术参数	参数描述
SN74V263-10PZA	功能描述:先进先出 8192 x 18 Synch 先进先出 Memory RoHS:否制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装:
SN74V263-15GGM	功能描述:先进先出 8192 x 18 Synch 先进先出 Memory RoHS:否制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装:
SN74V263-15PZA	功能描述:先进先出 8192 x 18 Synch 先进先出 Memory RoHS:否制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装:
SN74V263-6GGM	功能描述:先进先出 8192 x 18 Synch 先进先出 Memory RoHS:否制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装:
SN74V263-6PZA	功能描述:先进先出 8192 x 18 Synch 先进先出 Memory RoHS:否制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装:

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式