MOTOROLA
MC68HC16Z1
40
MC68HC16Z1TS/D
2.7.2 Exception Stack Frame
During exception processing, the contents of the program counter and condition code register are
stacked at a location pointed to by SK : SP. Unless it is altered during exception processing, the stacked
PK : PC value is the address of the next instruction in the current instruction stream, plus $0006. The
following figure shows the exception stack frame.
Figure 7 Exception Stack Frame
2.7.3 Exception Processing Sequence
Exception processing is performed in four distinct phases.
Priority of all pending exceptions is evaluated, and the highest priority exception is processed first.
Processor state is stacked, then the CCR PK extension field is cleared.
An exception vector number is acquired and converted to a vector address.
The content of the vector address is loaded into the PC, and the processor jumps to the exception
handler routine.
There are variations within each phase for differing types of exceptions. However, all vectors but reset
contain 16-bit addresses, and the PK field is cleared. Exception handlers must be located within bank
0, or vectors must point to a jump table.
2.7.4 Types of Exceptions
Exceptions can be generated either internally or externally. External exceptions which are defined as
asynchronous, include interrupts, bus errors (BERR), breakpoints (BKPT), and resets (RESET). Inter-
nal exceptions, which are defined as synchronous, include the software interrupt (SWI) instruction, the
background (BGND) instruction, illegal instruction exceptions, and the divide-by-zero exception. Refer
Asynchronous exceptions occur without reference to CPU16 or IMB clocks, but exception processing
is synchronized. For all asynchronous exceptions but RESET, exception processing begins at the first
instruction boundary following recognition of an exception.
Synchronous exception processing is part of an instruction definition. Exception processing for synchro-
nous exceptions will always be completed, and the first instruction of the handler routine will always be
executed, before interrupts are detected.
Because of pipelining, the stacked return PK : PC value for asynchronous exceptions, other than RE-
SET, is equal to the address of the next instruction in the current instruction stream plus $0006. The
RTI instruction, which must terminate all exception handler routines, subtracts $0006 from the stacked
value in order to resume execution of the interrupted instruction stream. The value of PK : PC at the
time a synchronous exception executes is equal to the address of the instruction that causes the excep-
tion plus $0006. Since RTI always subtracts $0006 upon return, the stacked PK : PC must be adjusted
by the instruction that caused the exception so that execution will resume with the following instruction.
$0002 is added to the PK : PC value before it is stacked.
Low Address
SP After Exception Stacking
Condition Code Register
High Address
Program Counter
SP Before Exception Stacking