![](http://datasheet.mmic.net.cn/140000/SPAKXC16Z1MFC16_datasheet_5015162/SPAKXC16Z1MFC16_56.png)
MOTOROLA
MC68HC16Z1
56
MC68HC16Z1TS/D
In the MC68HC16Z1, the largest amount of data that can be transferred by a single bus cycle is an
aligned word. If the MCU transfers a long-word operand via a 16-bit port, the most significant operand
word is transferred on the first bus cycle and the least significant operand word on a following bus cycle.
The CPU16 can perform misaligned word transfers. This capability makes it software compatible with
the MC68HC11 CPU. The CPU16 treats misaligned long-word transfers as two misaligned word trans-
fers.
3.5.12 Operand Transfer Cases
The following table summarizes how operands are aligned for various types of transfers. OPn entries
are portions of a requested operand that are read or written during a bus cycle and are defined by SIZ1,
SIZ0, and ADDR0 for that bus cycle.
NOTES:
1. Operands in parentheses are ignored by the CPU16 during read cycles.
2. Three-byte transfer cases occur only as a result of a long word to byte transfer.
3. The CPU16 treats misaligned long-word transfers as two misaligned word transfers.
3.5.13 Chip Selects
Typical microcontrollers require additional hardware to provide external chip select signals. Twelve in-
dependently programmable chip selects provide fast two-cycle access to external memory or peripher-
als. Address block sizes of two Kbytes to one Mbyte can be selected. However, because ADDR[23:20]
= ADDR19 in the CPU16, 512-Kbyte blocks are the largest usable size.
Chip select assertion can be synchronized with bus control signals to provide output enable, read/write
strobes, or interrupt acknowledge signals. Logic can also generate DSACK signals internally. A single
DSACK generator is shared by all circuits. Multiple chip selects assigned to the same address and con-
trol must have the same number of wait states.
Chip selects can also be synchronized with the ECLK signal available on ADDR23.
When a memory access occurs, chip select logic compares address space type, address, type of ac-
cess, transfer size, and interrupt priority (in the case of interrupt acknowledge) to parameters stored in
chip select registers. If all parameters match, the appropriate chip select signal is asserted. Select sig-
nals are active low. Refer to the following block diagram of a single chip-select circuit.
Table 14 Operand Alignment
Transfer Case
SIZ1
SIZ0
ADDR0
DSACK1
DSACK0
DATA
[15:8]
DATA
[7:0]
Byte to 8-Bit Port
0
1
X
1
0
OP0
(OP0)
Byte to 16-Bit Port (Even)
0
1
0
X
OP0
(OP0)
Byte to 16-Bit Port (Odd)
0
1
0
X
(OP0)
OP0
Word to 8-Bit Port (Aligned)
1
0
1
0
OP0
(OP1)
Word to 8-Bit Port (Misaligned)
1
0
1
0
OP0
(OP0)
Word to 16-Bit Port (Aligned)
1
0
X
OP0
OP1
Word to 16-Bit Port (Misaligned)
1
0
1
0
X
(OP0)
OP0
3 Byte to 8-Bit Port (Aligned)2
1
0
1
0
OP0
(OP1)
3 Byte to 8-Bit Port (Misaligned)2
1
0
OP0
(OP0)
3 Byte to 16-Bit Port (Aligned)3
1
0
X
OP0
OP1
3 Byte to 16-Bit Port (Misaligned)2
1
0
X
(OP0)
OP0
Long Word to 8-Bit Port (Aligned)
0
1
0
OP0
(OP1)
Long Word to 8-Bit Port (Misaligned)3
1
0
1
0
OP0
(OP0)
Long Word to 16-Bit Port (Aligned)
0
X
OP0
OP1
Long Word to 16-Bit Port (Misaligned)3
1
0
1
0
X
(OP0)
OP0