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| 型号： | SPD6729QCE |
| 厂商： | INTEL CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PQFP208 |
| 封装： | MQFP-208 |
| 文件页数： | 24/116页 |
| 文件大小： | 1442K |
| 代理商： | SPD6729QCE |
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PCI-to-PC Card (PCMCIA) Controller — PD6729
Datasheet
15
Note:
All pin inputs are referenced to CORE_VDD, independently of their output supply voltage.
The drive-type (Drive) column describes the output drive-type of the pin (see DC specifications in
“Electrical Specifications” on page 93 for more information). Note that the drive type listed for an
input-only (I) pin is not applicable (–).
2.3
Pin Descriptions
Power Type
Output or Pull-up Power Source
1
+5V: powered from a 5-volt power supply (in
most systems, see description of +5V pin in
2
A_SOCKET_VCC: powered from the Socket
A VCC supply connecting to PCMCIA pins 17
and 51 of Socket A
3
B_SOCKET_VCC: powered from the Socket
B VCC supply connecting to PCMCIA pins 17
and 51 of Socket B
4
PCI_VCC: powered from the PCI bus power
supply
5
CORE_VDD: powered from the lowest
available logic supply, which in most systems
is 3.3 volts
Table 1.
PCI Bus Interface Pins (Sheet 1 of 3)
Pin Name
Description
Pin Number
Qty.
I/O
Pwr.
Drive
AD[31:0]
PCI Bus Address Inputs / Data Input/Outputs:
These pins connect to PCI bus signals AD[31:0].
4-5, 7-12, 16-
20, 22-24, 38-
43, 45-46, 48-
49, 51-55, 57
32
I/O
4
PCI
Spec.
C/BE[3:0]#
PCI Bus Command / Byte Enables: The command
signalling and byte enables are multiplexed on the
same pins. During the address phase of a
transaction, C/BE[3:0]# are interpreted as the bus
commands. During the data phase, C/BE[3:0]# are
interpreted as byte enables. The byte enables are to
be valid for the entirety of each data phase, and they
indicate which bytes in the 32-bit data path are to
carry meaningful data for the current data phase.
13, 25, 36, 47
4
I
––
FRAME#
Cycle Frame: This input indicates to the PD6729 that
a bus transaction is beginning. While FRAME# is
asserted, data transfers continue. When FRAME# is
deasserted, the transaction is at its final phase.
27
1
I
––
IRDY#
Initiator Ready: This input indicates the initiating
agent’s ability to complete the current data phase of
the transaction. IRDY# is used in conjunction with
TRDY#.
29
1
I
––
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