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参数资料
| 型号： | SPD6729QCE |
| 厂商： | INTEL CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PQFP208 |
| 封装： | MQFP-208 |
| 文件页数： | 49/116页 |
| 文件大小： | 1442K |
| 代理商： | SPD6729QCE |
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PD6729 — PCI-to-PC Card (PCMCIA) Controller
38
Datasheet
Bit 6: Parity Error Check/Report Enable
This bit enables all parity-reporting-related circuitry, except for bit 31 of this register.
Bit 7: Wait Cycle Enable
This bit always reads a ‘1’, indicating that the PD6729 employs address stepping.
Bit 8: System Error (SERR#) Enable
This bit enables the PD6729’s reporting of system errors by assertion of the SERR# pin when
address parity errors occur. Bit 6 must also be set to a ‘1’ to allow detecting of conditions that allow
SERR# activation. See also description of bit 30.
Bit 24: Master Data Parity Error Reported
This bit is Reserved and will always read a ‘0’.
Bits 26-25: DEVSEL# Timing
This field always reads back ‘10’, identifying the PD6729 as a slow-speed device.
Bits 29-27: Reserved
These bits are reserved for future use. On writes to this register, these bits should be written as ‘0’.
The value of these bits should be considered as indeterminate on reads of this register.
Bit 30: System Error (SERR#) Generated
This bit is set whenever the PD6729 asserts SERR# because of internal detection of a PCI address
parity error. Bit 8 of this register must be set before system errors can be reported, and bit 6 must be
set to allow address parity errors to be detected. The PD6729 only asserts SERR# if address parity
errors occur. No other chip or system actions will cause SERR# to be driven active.
Bit 31: Address/Data Parity Error Detected
This bit indicates whether a parity error was detected, independently of whether bit 6 of this
register is a ‘1’.
0
Parity checking and reporting in the PD6729 disabled.
1
Parity checking and reporting in the PD6729 is enabled.
0
Activation of SERR# on address parity error is disabled.
1
SERR# is activated whenever an address parity error is internally detected (slave mode).
0
SERR# was not asserted by this device.
1
SERR# was asserted by this device, indicating a PCI address parity error.
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