参数资料
型号: SPD6729QCE
厂商: INTEL CORP
元件分类: 总线控制器
英文描述: PCMCIA BUS CONTROLLER, PQFP208
封装: MQFP-208
文件页数: 54/116页
文件大小: 1442K
代理商: SPD6729QCE
PD6729 — PCI-to-PC Card (PCMCIA) Controller
42
Datasheet
5.6
Interrupt Line, Interrupt Pin, Min_Gnt, and Max_Lat
Bits 7-0: Interrupt Line
For other than PCMCIA-controller-type PCI devices, this field indicates interrupt line routing.
Although this register is read/write for PCI compatibility, no interrupt line routing is controlled by
this register on the PD6729. Because the PD6729 must dynamically configure interrupt usage, the
actual routing to the appropriate interrupt line is made by writing to interrupt-type-specific
interrupt control bit settings in the Operation registers (see the Interrupt and General Control
register).
Bits 15-8: Interrupt Pin
For other than PCMCIA-controller-type PCI devices, this read-only field indicates which interrupt
pin the device uses. Because the PD6729 must dynamically configure interrupt usage, the actual
connection of interrupt pins is defined by interrupt control bit settings in the Operation registers
(see the Management Interrupt Configuration register). This field always reads back 01h.
Bits 31-24: Max_Lat
This field indicates the maximum time that can occur between PCI bus accesses to the PD6729
while still efficiently performing transfers to or from PCMCIA cards. The value programmed is in
250-ns increments, based on full-speed PCI_CLK operation. This field always reads back 00h,
indicating that there are no major latency requirements.
Configuration Register Name: Interrupt Line, Interrupt Pin, Min_Gnt, and Max_Lat
Offset: 3Ch
Register Per: chip
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Byte 3
Max_Lat
Max_Lat
R:00000000
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Byte 2
Min_Gnt
Reserved
R:XXXXXXXX
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Byte 1
Interrupt
Pin
Interrupt Pin
R:00000001
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 0
Interrupt
Line
Interrupt Line
RW:00000000
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