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参数资料
| 型号： | SPD6729QCE |
| 厂商： | INTEL CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PQFP208 |
| 封装： | MQFP-208 |
| 文件页数： | 42/116页 |
| 文件大小： | 1442K |
| 代理商： | SPD6729QCE |
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PCI-to-PC Card (PCMCIA) Controller — PD6729
Datasheet
31
3.1.7
Write FIFO
To increase performance when writing to PCMCIA cards, two, independent, four-word-deep write
FIFOs are used. Writes to PCMCIA cards will complete without holding off the PCI bus until the
FIFO is full.
Note:
Register states should only be changed when the write FIFO is empty.
3.1.8
Bus Sizing
The PD6729 operates in 32-bit mode. All PCI transactions are 32-bit, even when supporting 8-bit-
only or 16-bit PCMCIA cards.
3.1.9
Programmable PCMCIA Timing
The Setup, Command, and Recovery time for the PCMCIA bus is programmable (see “Timing
Registers” on page 87). The PD6729 can be programmed to match the timing requirements of any
PCMCIA card. There are two sets of timing registers, Timer Set 0 and Timer Set 1, that can be
selected on a per-window basis for both I/O and memory windows.
By setting one of the timing sets for a Recovery time equal to flash memory programming time and
utilizing the write FIFO, algorithms can be created to relieve system software of the necessity of
doing timing loops, and thus allow for flash programming in the background.
3.1.10
ATA Mode Operation
The PD6729 supports direct connection to AT-attached-interface hard drives. ATA drives use an
interface very similar to the IDE interface found on many popular portable computers. See “ATA
Mode Operation” on page 91 for more information.
3.1.11
VS1 and VS2
The pins VS1 and VS2 can be used to determine the voltage capabilities of an inserted card. The
status of these pins, for both sockets, are indicated by bits 3:0 of the External Data register at
extended index 0Ah of index 6Fh (this is true even though registers 40h–7Fh are generally for
Socket B only).
3.2
Host Access to Registers
The PD6729 registers are accessed through an 8-bit indexing mechanism. An index register scheme
allows a large number of internal registers to be accessed by the CPU using only two I/O addresses.
The Index register (see “Operation Registers” on page 43) is used to specify which of the internal
registers the CPU will access next. The value in the Index register is called the Register Index and
is the number that specifies a unique internal register. The Data register is used by the CPU to read
and write the internal register specified by the Index register.
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