ST7267C8 ST7267R8
44/189
ST7 INTERRUPTS (Cont’d)
Bits 7:0 = ITxE Port A interrupt enable
These bits are set and cleared by software.
0: ITx external interrupt disabled.
1: ITx external interrupt enabled.
PORT B EXTERNAL INTERRUPT ENABLE
REGISTER (PBEIENR)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = ITxE Port B interrupt enable
These bits are set and cleared by software.
0: ITx external interrupt disabled.
1: ITx external interrupt enabled.
PORT C EXTERNAL INTERRUPT ENABLE
REGISTER (PCEIENR)
Read/Write
Reset Value: 0000 0000 (00h)
These bits are set and cleared by software.
Bits 7:0 = ITxE Port C interrupt enable
0: ITx external interrupt disabled.
1: ITx external interrupt enabled.
PORT D EXTERNAL INTERRUPT ENABLE
REGISTER (PDEIENR)
Read/Write
Reset Value: 0000 0000 (00h)
These bits are set and cleared by software.
Bits 7:0 = ITxE Port D interrupt enable
0: ITx external interrupt disabled.
1: ITx external interrupt enabled.
PORT E EXTERNAL INTERRUPT ENABLE
REGISTER (PEEIENR)
Read/Write
Reset Value: 0000 0000 (00h)
These bits are set and cleared by software.
Bits 7:0 = ITxE Port E interrupt enable
0: ITx external interrupt disabled.
1: ITx external interrupt enabled.
PORT A EXTERNAL INTERRUPT STATUS
REGISTER (PAEISR)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = ITxF Port A interrupt flag
These bits are set by hardware and cleared by
software (by writing 0).
0: ITx external interrupt not requested.
1: ITx external interrupt requested.
PORT B EXTERNAL INTERRUPT STATUS
REGISTER (PBEISR)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = ITxF Port B interrupt flag
These bits are set by hardware and cleared by
software (by writing 0).
0: ITx external interrupt not requested.
1: ITx external interrupt requested.
70
IT15E IT14E IT13E IT12E IT11E IT10E IT9E
IT8E
70
IT23E IT22E IT21E IT20E IT19E IT18E IT17E IT16E
70
IT31E IT30E IT29E IT28E IT27E IT26E IT25E IT24E
70
IT39E IT38E IT37E IT36E IT35E IT34E IT33E IT32E
70
IT7F
IT6F
IT5F
IT4F
IT3F
IT2F
IT1F
IT0F
70
IT15F IT14F IT13F IT12F IT11F IT10F IT9F
IT8F