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参数资料
| 型号： | ST7267R8T1L/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封装： | 10 X 10 MM, LEAD FREE, TQFP-64 |
| 文件页数： | 8/189页 |
| 文件大小： | 1643K |
| 代理商： | ST7267R8T1L/XXX |
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ST7267C8 ST7267R8
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point 0. These are described in the Universal Seri-
al Bus Specification, Revision 2.0, Chapter 9. The
protocol for these device requests involves differ-
ent numbers and types of transaction per transfer.
To accommodate this, application software needs
to take a state machine approach to command de-
coding and handling.
The Standard Device Requests can be divided
into three categories: Zero Data Requests (in
which all the information is included in the com-
mand), Write Requests (in which the command will
be followed by additional data), and Read Re-
quests (in which the device is required to send
data back to the host).
This section looks at the sequence of events that
the software must perform to process the different
types of device request.
10.5.10.1 Endpoint 0 Service Routine
An Endpoint 0 interrupt is generated:
■ When the core sets the OPR bit (CSR0) after a
valid token has been received and data has
been written to the FIFO.
■ When the core clears the IPR bit (CSR0) after
the packet of data in the FIFO has been
successfully transmitted to the host.
■ When the core sets the STST bit (CSR0) after a
control transaction is ended due to a protocol
violation.
■ When the core sets the SE bit (CSR0) because
a control transfer has ended before DE (CSR0)
is set.
Whenever the Endpoint 0 service routine is en-
tered, the software must first check to see if the
current control transfer has been ended due to ei-
ther a STALL condition or a premature end of con-
trol transfer. If the control transfer ends due to a
STALL condition, the STST bit is set. If the control
transfer ends due to a premature end of control
transfer, the SE bit is set. In either case, the soft-
ware should abort processing the current control
transfer and set the state to IDLE.
10.5.10.2 Error Handling
A control transfer may be aborted due to a protocol
error on the USB, the host prematurely ending the
transfer, or if the function controller software wish-
es to abort the transfer (e.g. because it cannot
process the command).
The USB controller will automatically detect proto-
col errors and send a STALL packet to the host un-
der the following conditions:
1. Host sends more data during the OUT Data
phase of a write request than was specified in the
command. This condition is detected when the
host sends an OUT token after the DE bit (CSR0)
has been set.
2. Host requests more data during the IN Data
phase of a read request than was specified in the
command. This condition is detected when the
host sends an IN token after the DE bit in the
CSR0 register has been set.
3. Host sends more than MaxP data bytes in an
OUT data packet.
4. Host sends a non-zero length DATA1 packet
during the STATUS phase of a read request.
When the USB controller has sent the STALL
packet, it sets the STST bit (CSR0) and generates
an interrupt. When the software receives an End-
point 0 interrupt with the STST bit set, it should
abort the current transfer, clear the SentStall bit,
and return to the IDLE state.
If the host prematurely ends a transfer by entering
the STATUS phase before all the data for the re-
quest has been transferred, or by sending a new
SETUP packet before completing the current
transfer, then the SE bit (CSR0) will be set and an
Endpoint 0 interrupt generated. When the software
receives an Endpoint 0 interrupt with the SE bit
set, it should abort the current transfer, set the
SSE bit (CSR0), and return to the IDLE state. If the
OPR bit (CSR0) is set this indicates that the host
has sent another SETUP packet and the software
should then process this command.
10.5.11 Bulk IN Endpoint
A Bulk IN endpoint is used to transfer non-periodic
data from the function controller to the host.
Three optional features are available for use with a
Bulk IN endpoint:
■ Double packet buffering
If the value written to the INMAXPR register is less
than, or equal to, half the size of the FIFO allocat-
ed to the endpoint, double packet buffering will be
automatically enabled. When enabled, up to two
packets can be stored in the FIFO awaiting trans-
mission to the host.
■ DMA
If DMA is enabled for the endpoint, a DMA request
will be generated whenever the endpoint is able to
accept another packet in its FIFO. This feature is
used to allow transfer to the MSCI without ST7 in-
tervention in order to allow high speed transfer to/
from the USB controller.
■ AutoSet
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