- 您现在的位置：买卖IC网 > PDF目录98145 > ST72774S9T1/XXX (STMICROELECTRONICS) 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP44 PDF资料下载
参数资料
| 型号： | ST72774S9T1/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP44 |
| 封装： | TQFP-44 |
| 文件页数： | 133/144页 |
| 文件大小： | 1280K |
| 代理商： | ST72774S9T1/XXX |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页当前第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页
ST72774/ST727754/ST72734
89/144
IC SINGLE MASTER BUS INTERFACE (Cont’d)
4.7.4 Functional Description (Master Mode)
Refer to the CR, SR1 and SR2 registers in Section
4.7.5. for the bit definitions.
By default the I2C interface operates in idle mode
(M/IDL bit is cleared) except when it initiates a
transmit or receive sequence.
To switch from default idle mode to Master mode a
Start condition generation is needed.
Start condition and Transmit Slave address
Setting the START bit causes the interface to
switch to Master mode (M/IDL bit set) and
generates a Start condition.
Once the Start condition is sent:
– The EVF and SB bits are set by hardware with
an interrupt if the ITE bit is set.
Then the master waits for a read of the SR1
register followed by a write in the DR register with
the Slave address byte, holding the SCL line low
(see Figure 54 Transfer sequencing EV1).
Then the slave address byte is sent to the SDA line
via the internal shift register.
After completion of this transfer (and acknowledge
from the slave if the ACK bit is set):
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
Then the master waits for a read of the SR1
register followed by a write in the CR register (for
example set PE bit), holding the SCL line low
(see Figure 54 Transfer sequencing EV2).
Next
the
master
must
enter
Receiver
or
Transmitter mode.
Master Receiver
Following the address transmission and after SR1
and CR registers have been accessed, the master
receives bytes from the SDA line into the DR
register via the internal shift register. After each
byte the interface generates in sequence:
– Acknowledge pulse if if the ACK bit is set
– EVF and BTF bits are set by hardware with an in-
terrupt if the ITE bit is set.
Then the interface waits for a read of the SR1
register followed by a read of the DR register,
holding the SCL line low (see Figure 54 Transfer
sequencing EV3).
To close the communication: before reading the
last byte from the DR register, set the STOP bit to
generate the Stop condition. The interface goes
automatically back to idle mode (M/IDL bit
cleared).
Note: In order to generate the non-acknowledge pulse af-
ter the last received data byte, the ACK bit must be
cleared just before reading the second last data
byte.
Master Transmitter
Following the address transmission and after SR1
register has been read, the master sends bytes
from the DR register to the SDA line via the internal
shift register.
The master waits for a read of the SR1 register
followed by a write in the DR register, holding the
SCL line low (see Figure 54 Transfer sequencing
EV4).
When the acknowledge bit is received, the
interface sets:
– EVF and BTF bits with an interrupt if the ITE bit
is set.
To close the communication: after writing the last
byte to the DR register, set the STOP bit to
generate the Stop condition. The interface goes
automatically back to idle mode (M/IDL bit
cleared).
Error Case
– AF: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set by hardware
with an interrupt if the ITE bit is set. To resume,
set the START or STOP bit.
Note: The SCL line is not held low.
相关PDF资料 |
PDF描述 |
|---|---|
| ST72E734J6D0 | 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CDIP42 |
| ST72T774S9T1 | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP44 |
| ST7294C6B6 | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDIP28 |
| ST72T94C6M6 | 8-BIT, OTPROM, MICROCONTROLLER, PDSO28 |
| ST72C171K2B6 | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ST727X4-EMU2B | 制造商:STMicroelectronics 功能描述:REALTIME EMULATOR BOARD - Bulk |
| ST727X4-EPB/US | 制造商:STMicroelectronics 功能描述:PROGRAMMER - Bulk |
| ST-7-28 | 功能描述:XFRMR PWR 115V 14VAC 2.6A RoHS:是 类别:变压器 >> 功率 系列:ST 标准包装:1 系列:260 类型:标准 最大功率:65 VA 主线圈:双 副线圈:三路，中心抽头 在某电流时的串联输出电压:500 VAC @ 85mA，5 VAC @ 2A，6.3 VAC @ 2A 在某电流时的并联输出电压:- 安装类型:底座安装 尺寸/尺寸:102.36mm L x 67.31mm W 高度 - 座高（最大）:66.80mm 端接类型:导线引线 |
| ST7-28 | 制造商:SUPERWORLD 制造商全称:Superworld Electronics 功能描述:POWER TRANSFORMER |
| ST7-28B56 | 功能描述:电源变压器 SPLIT BOBBIN HORZ MOUNT XFMR RoHS:否 制造商:Triad Magnetics 功率额定值:12 VA 初级电压额定值:115 V / 230 V 次级电压额定值:12 V / 24 V 安装风格:SMD/SMT 一次绕组:Dual Primary Winding 二次绕组:Dual Secondary Winding 长度:2.5 in 宽度:2 in 高度:1.062 in |
发布紧急采购，3分钟左右您将得到回复。