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参数资料
| 型号： | ST72774S9T1/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP44 |
| 封装： | TQFP-44 |
| 文件页数： | 15/144页 |
| 文件大小： | 1280K |
| 代理商： | ST72774S9T1/XXX |
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ST72774/ST727754/ST72734
111/144
DDC INTERFACE (Cont’d)
DDC STATUS REGISTER 1 (SR1)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7 = EVF
Event flag.
This bit is set by hardware as soon as an event
occurs. It is cleared by software reading SR2
register in case of error event or as described in
Figure 67. It is also cleared by hardware when the
interface is disabled (PE=0).
0: No event
1: One of the following events has occurred:
– BTF=1 (Byte received or transmitted)
– ADSL=1 (Address matched in Slave mode
while ACK=1)
– AF=1 (No acknowledge received after byte
transmission if ACK=1)
– STOPF=1 (Stop condition detected in Slave
mode)
– BERR=1 (Bus error, misplaced Start or Stop
condition detected)
Bit 6 = Reserved. Forced to 0 by hardware.
Bit 5 = TRA
Transmitter/Receiver.
When BTF is set, TRA=1 if a data byte has been
transmitted. It is cleared automatically when BTF
is cleared. It is also cleared by hardware after
detection of Stop condition (STOPF=1) or when
the interface is disabled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
Bit 4 = BUSY
Bus busy.
This bit is set by hardware on detection of a Start
condition and cleared by hardware on detection of
a Stop condition. It indicates a communication in
progress on the bus. This information is still
updated when the interface is disabled (PE=0).
0: No communication on the bus
1: Communication ongoing on the bus
Bit 3 = BTF
Byte transfer finished.
This bit is set by hardware as soon as a byte is
correctly received or transmitted with interrupt
generation if ITE=1. It is cleared by software
reading SR1 register followed by a read or write of
DR register. It is also cleared by hardware when
the interface is disabled (PE=0).
– Following a byte transmission, this bit is set after
reception of the acknowledge clock pulse. . BTF
is cleared by reading SR1 register followed by
writing the next byte in DR register.
– Following a byte reception, this bit is set after
transmission of the acknowledge clock pulse if
ACK=1. BTF is cleared by reading SR1 register
followed by reading the byte from DR register.
The SCL line is held low while BTF=1.
0: Byte transfer not done
1: Byte transfer succeeded
Bit 2 = ADSL
Address matched (Slave mode). This
bit is set by hardware as soon as the received
slave address matched with the OAR register
content
or
the
Enhanced
DDC
address
is
recognized. An interrupt is generated if ITE=1. It is
cleared by software reading SR1 register or by
hardware when the interface is disabled (PE=0).
The SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
Bit 1:0 = Reserved. Forced to 0 by hardware.
70
EVF
0
TRA
BUSY
BTF
ADSL
0
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