- 您现在的位置：买卖IC网 > PDF目录98145 > ST72774S9T1/XXX (STMICROELECTRONICS) 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP44 PDF资料下载
参数资料
| 型号： | ST72774S9T1/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP44 |
| 封装： | TQFP-44 |
| 文件页数： | 60/144页 |
| 文件大小： | 1280K |
| 代理商： | ST72774S9T1/XXX |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页当前第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页
ST72774/ST727754/ST72734
22/144
3.3 INTERRUPTS
The ST727x4 may be interrupted by one of two
different methods: maskable hardware interrupts
as listed in Table 6 and a non-maskable software
interrupt
(TRAP).
The
Interrupt
processing
flowchart is shown in Figure 13.
The maskable interrupts must be enabled in order
to be serviced. However, disabled interrupts can
be latched and processed when they are enabled.
When an interrupt has to be serviced, the PC, X, A
and CC registers are saved onto the stack and the
interrupt mask (I bit of the Condition Code
Register) is set to prevent additional interrupts.
The Y register is not automatically saved.
The PC is then loaded with the interrupt vector of
the interrupt to service and the interrupt service
routine runs (refer to Table 6, “Interrupt Mapping,”
on page 24 for vector addresses). The interrupt
service routine should finish with the IRET
instruction which causes the contents of the
registers to be recovered from the stack and
normal processing to resume. Note that the I bit is
then cleared if and only if the corresponding bit
stored in the stack is zero.
Though many interrupts can be simultaneously
pending, a priority order is defined (see Table 6,
“Interrupt Mapping,” on page 24). The RESET pin
has the highest priority.
If the I bit is set, only the TRAP interrupt is enabled.
All interrupts allow the processor to leave the
WAIT low power mode.
Software Interrupt. The software interrupt is the
executable instruction TRAP. The interrupt is
recognized
when
the
TRAP
instruction
is
executed, regardless of the state of the I bit. When
the interrupt is recognized, it is serviced according
to the flowchart on Figure 13.
ITA, ITB interrupts. The ITA (PD3), ITB (PD4),
pins can generate an interrupt when a falling edge
occurs on these pins, if these interrupts are
enabled with the ITAITE, ITBITE bits respectively
in the miscellaneous register and the I bit of the CC
register is reset. When an enabled interrupt
occurs, normal processing is suspended at the
end of the current instruction execution. It is then
serviced according to the flowchart on Figure 13.
Software in the ITA or ITB service routine must
reset the cause of this interrupt by clearing the
ITALAT, ITBLAT or ITAITE, ITBITE bits in the
miscellaneous register.
Peripheral
Interrupts.
Different
peripheral
interrupt flags are able to cause an interrupt when
they are active if both the I bit of the CC register is
reset and if the corresponding enable bit is set. If
either of these conditions is false, the interrupt is
latched and thus remains pending.
The interrupt flags are located in the status
register. The Enable bits are in the control register.
When
an
enabled
interrupt
occurs,
normal
processing is suspended at the end of the current
instruction execution. It is then serviced according
to the flowchart on Figure 13.
The general sequence for clearing an interrupt is
an access to the status register while the flag is set
followed by a read or write of an associated
register. Note that the clearing sequence resets
the internal latch. A pending interrupt (i.e. waiting
for being enabled) will therefore be lost if the clear
sequence is executed.
相关PDF资料 |
PDF描述 |
|---|---|
| ST72E734J6D0 | 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CDIP42 |
| ST72T774S9T1 | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP44 |
| ST7294C6B6 | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDIP28 |
| ST72T94C6M6 | 8-BIT, OTPROM, MICROCONTROLLER, PDSO28 |
| ST72C171K2B6 | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ST727X4-EMU2B | 制造商:STMicroelectronics 功能描述:REALTIME EMULATOR BOARD - Bulk |
| ST727X4-EPB/US | 制造商:STMicroelectronics 功能描述:PROGRAMMER - Bulk |
| ST-7-28 | 功能描述:XFRMR PWR 115V 14VAC 2.6A RoHS:是 类别:变压器 >> 功率 系列:ST 标准包装:1 系列:260 类型:标准 最大功率:65 VA 主线圈:双 副线圈:三路，中心抽头 在某电流时的串联输出电压:500 VAC @ 85mA，5 VAC @ 2A，6.3 VAC @ 2A 在某电流时的并联输出电压:- 安装类型:底座安装 尺寸/尺寸:102.36mm L x 67.31mm W 高度 - 座高（最大）:66.80mm 端接类型:导线引线 |
| ST7-28 | 制造商:SUPERWORLD 制造商全称:Superworld Electronics 功能描述:POWER TRANSFORMER |
| ST7-28B56 | 功能描述:电源变压器 SPLIT BOBBIN HORZ MOUNT XFMR RoHS:否 制造商:Triad Magnetics 功率额定值:12 VA 初级电压额定值:115 V / 230 V 次级电压额定值:12 V / 24 V 安装风格:SMD/SMT 一次绕组:Dual Primary Winding 二次绕组:Dual Secondary Winding 长度:2.5 in 宽度:2 in 高度:1.062 in |
发布紧急采购，3分钟左右您将得到回复。