2-8
Functional Descriptions
2.1.7.3 Select Control (SSEL)
A_SSEL and B_SSEL are control signals used during bus arbitration and
selection. Whichever side asserts, SSEL propagates it to the other side.
If both signals are asserted at the same time, the A Side receives SSEL
and sends it to the B Side. This output has pull-down control for an open
collector driver. The processing steps for the signals are:
1.
The input signal is blocked if it is being driven by the SYM53C180.
2.
The next stage is a leading edge lter. This ensures that the output
does not switch for a specied time after the leading edge. The
duration of the input signal then determines the duration of the
output.
3.
A parallel function ensures that bus (transmission line) recovery
occurs for a specied time after the last signal deassertion on each
signal line.
2.1.7.4 Busy Control (SBSY)
A_SBSY and B_SBSY signals are propagated from the source bus to the
load bus. The busy control signals go through this process:
1.
The bus is tested to ensure the signal if being driven by the
SYM53C180 is not misinterpreted as an incoming signal.
2.
The data is then leading edge ltered. The assertion edge is held for
a specied time to prevent any signal bounce. The input signal
controls the duration.
3.
The signal path switches the long and short lters used in the circuit
depending upon the current state of the SYM53C180. The current
state of the SYM53C180 State Machine that tracks SCSI phases
selects the mode. The short lter mode passes data through, while
the long lter mode indicates the bus free state. When the Busy
(SBSY) and Select (SSEL) sources switch from side to side, the long
lter mode is used. This output is then fed to the output driver, which
is a pull-down open collector only.
4.
A parallel function ensures that bus (transmission line) recovery is
available for a specied time after the last signal deassertion on each
signal line.