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参数资料
| 型号： | SYM53C180I2 |
| 厂商： | LSI CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | SCSI BUS CONTROLLER, PBGA192 |
| 封装： | 23 X 23 MM, 1.27 MM PITCH, PLASTIC, BGA-192 |
| 文件页数： | 25/78页 |
| 文件大小： | 1073K |
| 代理商： | SYM53C180I2 |
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Interface Signal Descriptions
2-13
pass from one bus to the other. The signal is asserted HIGH when the
chip is active.
2.1.8.4 Clock (CLOCK)
This is the 40 MHz oscillator input to the SYM53C180. It is the clock
source for the protocol control state machines and timing generation
logic. This clock is not used in any bus signal transfer paths.
2.1.9 SCSI Termination
The terminator networks provide the biasing needed to pull signals to an
inactive voltage level, and to match the impedance seen at the end of
the cable with the characteristic impedance of the cable. Terminators
must be installed at the extreme ends of each SCSI segment, and only
at the ends. No SCSI segment should ever have more or less than two
terminators installed and active. SCSI host adapters should provide a
means of accommodating terminators. The terminators should be
socketed, so they may be removed if not needed. Otherwise, the
terminators should be disabled by software means.
Multimode terminators are required because they provide both LVD and
SE termination, depending on what mode of operation is detected by the
DIFFSENS pins.
Important:
LSI Logic recommends that active termination be used for
the bus connections to the SYM53C180. The Unitrode
5630 or Dallas 2108 commonly used for Ultra2 buses can
also be used interchangeably for Ultra3. The Unitrode 5628
can be used for Ultra3 and allows use of two devices on
the SCSI bus rather than three.
Table 2.5
XFER_ACTIVE Signal Polarity
Signal Level
State
Effect
HIGH = 1
Asserted
Indicates normal operation, and transfers through
the SYM53C180 are enabled.
LOW = 0
Deasserted
The SYM53C180 has detected a Bus Free state
due to WS_ENABLE being low, thus disabling
transfers through the device.
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