参数资料
型号: SYM53C180I2
厂商: LSI CORP
元件分类: 总线控制器
英文描述: SCSI BUS CONTROLLER, PBGA192
封装: 23 X 23 MM, 1.27 MM PITCH, PLASTIC, BGA-192
文件页数: 27/78页
文件大小: 1073K
代理商: SYM53C180I2
Internal Control Descriptions
2-15
2.2.2.2 REQ/ACK
These input clock signals get edge ltered and stretched to minimum
values to avoid glitches. In double transition clocking, both leading and
trailing edges are ltered, while only the leading edge is ltered in single
transition clocking. These lters provide edge ltering to remove noise
within the initial signal transition. The current transmission speed selects
the time values.
2.2.3 Busy Filters
The busy control signal passes from source to load bus with ltering
selected by the current state of the SCSI bus. This lter provides a
synchronized leading edge signal that is not true until the input signal
has been stable. The trailing edge occurs within several nanoseconds of
the input being deasserted. When the BSY signal is asserted before and
after the SEL signal, the lter is on.
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