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| 型号： | SYM53C180I2 |
| 厂商： | LSI CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | SCSI BUS CONTROLLER, PBGA192 |
| 封装： | 23 X 23 MM, 1.27 MM PITCH, PLASTIC, BGA-192 |
| 文件页数： | 8/78页 |
| 文件大小： | 1073K |
| 代理商： | SYM53C180I2 |
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1-6
Introduction
1.1.3 Specications
40 MHz Input Clock
192-pin Plastic Ball Grid Array package (PBGA). This package is a
drop in replacement for the SYM53C140 when the design uses the
SYM53C180 pin out.
Compliant with the SCSI Parallel Interface-3 (SPI-3)
Compliant with SCSI Enhanced Parallel Interface (EPI) Specifications
1.2 Ultra3 SCSI
The SYM53C180 SCSI Bus Expander supports Ultra3 SCSI. This
interface is an extension of the SCSI-3 standards that expands the
bandwidth of the SCSI bus to allow faster synchronous data transfers,
up to 160 Mbytes/s. Ultra3 SCSI provides a doubling of the data rate
over the Ultra2 SCSI interface. All new speeds after Ultra2 are wide.
1.2.1 Double Transition Clocking
Ultra3 provides double transition clocking for LVD transfers where
clocking is dened on the rising and falling edges of the clock. The
latching of data on both the assertion edge and the negation edge of the
REQ/ACK signal represents Double Transition (DT) data phases. DT
data phase encompasses both the DT Data In and the DT Data Out
phase. DT data phases use only 16-bit, synchronous transfers.
Information unit and data group transfers use DT data phases to transfer
data. Information unit transfers transmit all nexus, task management,
task attribute, command, data, and protection. Data group transfers
transmit all data and protection. The number of bytes transferred for an
information unit or data group is always a multiple of four. Refer to the
SCSI Parallel Interface-3 (SPI-3) for more detailed information about
double transition clocking.
1.2.2 Cyclic Redundancy Check (CRC)
Ultra3 supports Cyclic Redundancy Checking, which represents error
checking code to detect the validity of data. CRC increases the reliability
of data transfers since four bytes of code are transferred along with data.
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