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参数资料
| 型号： | TLV320AIC3111IRHBT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 音频／视频放大 |
| 英文描述： | AUDIO AMPLIFIER, PQCC32 |
| 封装： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件页数： | 126/156页 |
| 文件大小： | 1701K |
| 代理商： | TLV320AIC3111IRHBT |
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BCLK
WCLK
DIN/DOUT
n-1 n-2
1
0
n-1 n-2
1
0
LSB
MSB
LeftChannel
RightChannel
n-3
2
n-3
LSB
MSB
1/fs
www.ti.com
SLAS644B – JULY 2009 – REVISED OCTOBER 2009
The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in master
mode, this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider
in page 0 / register 30 (see Figure 5-36). The number of bit-clock pulses in a frame may need adjustment
to accommodate various word lengths as well as to support the case when multiple TLV320AIC3111s may
share the same audio bus.
The TLV320AIC3111 also includes a feature to offset the position of start of data transfer with respect to
the word clock. This offset can be controlled in terms of number of bit-clocks and can be programmed in
page 0 / register 28.
The TLV320AIC3111 also has the feature of inverting the polarity of the bit clock used for transferring the
audio data as compared to the default clock polarity used. This feature can be used independently of the
mode of audio interface chosen. This can be configured via page 0 / register 29, bit D3.
The TLV320AIC3111 further includes programmability (page 0 / register 27, bit D0) to place the DOUT line
in the high-impedance state during all bit clocks when valid data is not being sent. By combining this
capability with the ability to program at what bit clock in a frame the audio data begins, time-division
multiplexing (TDM) can be accomplished, enabling the use of multiple codecs on a single audio serial data
bus. When the audio serial data bus is powered down while configured in master mode, the pins
associated with the interface are put into a high-impedance output condition. Also, DOUT control on
page 0 / register 53, bit D4 allows the bus-keeper feature to be enabled/disabled. When enabled, the last
valid data on DOUT is held (weakly driven) during the non-data time. When disabled, DOUT is placed in a
high-impeance state when page 0 / register 27, bit D0 is enabled (1).
By default, when the word clocks and bit clocks are generated by the TLV320AIC3111, these clocks are
active only when the codecs (ADC, DAC or both) are powered up within the device. This is done to save
power. However, it also supports a feature when both the word clocks and bit clocks can be active even
when the codec in the device is powered down. This is useful when using the TDM mode with multiple
codecs on the same bus, or when word clocks or bit clocks are used in the system as general-purpose
clocks.
5.8.1.1
Right-Justified Mode
The audio interface of the TLV320AIC3111 can be put into the right-justified mode by programming
page 0 / register 27, bits D7–D6 = 10. In right-justified mode, the LSB of the left channel is valid on the
rising edge of the bit clock preceding the falling edge of the word clock. Similarly, the LSB of the right
channel is valid on the rising edge of the bit clock preceding the rising edge of the word clock.
Figure 5-39. Timing Diagram for Right-Justified Mode
For the right-justified mode, the number of bit clocks per frame should be greater than or equal to twice
the programmed word length of the data.
Copyright 2009, Texas Instruments Incorporated
APPLICATION INFORMATION
71
Product Folder Link(s): TLV320AIC3111
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