SLAS644B – JULY 2009 – REVISED OCTOBER 2009
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Electrical Characteristics (continued)
At 25°C; AVDD, HPVDD, IOVDD = 3.3V; SPLVDD, SPRVDD = 3.6 V; DVDD = 1.8 V; fS (audio) = 48 kHz;
CODEC_CLKIN = 256 × fS; PLL = Off; VOL/MICDET pin disabled (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC Digital Interpolation Filter Characteristics
DAC Output to Class-D Speaker Output; Load = 8
(Differential), 50 pF
SPLVDD = SPRVDD = 3.6 V, BTL measurement, DAC
input = 0 dBFS, DAC VCM (page 1 / register 31, bits
2.2
D4–D3) = 1.65 V, class-D gain = 6 dB,
THD
≤ –16.5 dB
Output voltage
Vrms
SPLVDD = SPRVDD = 3.6 V, BTL measurement, DAC
input = –2 dBFS, DAC VCM (page 1 / register 31, bits
2.1
D4–D3) = 1.65 V, class-D gain = 6 dB, THD
≤ –20 dB
SPLVDD = SPRVDD = 3.6 V, BTL measurement, DAC
Output, common-mode
input = mute, DAC VCM (page 1 / register 31, bits D4–D3)
1.8
V
= 1.65 V, class-D gain = 6 dB
SPLVDD = SPRVDD = 3.6 V, BTL measurement, class-D
SNR
Signal-to-noise ratio
gain = 6 dB, measured as idle-channel noise, A-weighted
87
dB
(with respect to full-scale output value of 2.2 Vrms)(1) (2)
SPLVDD = SPRVDD = 3.6 V, BTL measurement, DAC
THD
Total harmonic distortion
input = –6 dBFS, DAC VCM (page 1 / register 31, bits
–67
dB
D4–D3) = 1.65 V, class-D gain = 6 dB
SPLVDD = SPRVDD = 3.6 V, BTL measurement, DAC
Total harmonic distortion +
THD+N
input = –6 dBFS, DAC VCM (page 1 / register 31, bits
–66
dB
noise
D4–D3) = 1.65 V, class-D gain = 6 dB
SPLVDD = SPRVDD = 3.6 V, BTL measurement, ripple on
PSRR
Power-supply rejection ratio(3)
–44
dB
SPLVDD/SPRVDD = 200 mVp-p at 1 kHz
Mute attenuation
110
dB
SPLVDD = SPRVDD = 3.6 V, BTL measurement, DAC
VCM (page 1 / register 31, bits D4–D3) = 1.65 V, class-D
540
gain = 18 dB, THD = 10%
mW
SPLVDD = SPRVDD = 4.3 V, BTL measurement, DAC
PO
Maximum output power
VCM (page 1 / register 31, bits D4–D3) = 1.65 V, class-D
790
gain = 18 dB, THD = 10%
SPLVDD = SPRVDD = 5.5 V, BTL measurement, DAC
VCM (page 1 / register 31, bits D4–D3) = 1.65 V, class-D
1.29
W
gain = 18 dB, THD = 10%
Output-stage leakage current
SPLVDD = SPRVDD = 4.3 V, device is powered down
80
nA
for direct battery connection
(power-up-reset condition)
ADC and DAC POWER CONSUMPTION
For ADC and DAC power consumption based on selected processing block, see
Section 5.4.(1)
Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
(2)
All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
(3)
DAC to speaker-out PSRR is a differential measurement calculated as PSRR = 20 × log(
ΔVSPL(P + M) / ΔVSPLVDD).
8
ELECTRICAL SPECIFICATIONS
Copyright 2009, Texas Instruments Incorporated