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| 型号： | TLV320AIC3111IRHBT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 音频／视频放大 |
| 英文描述： | AUDIO AMPLIFIER, PQCC32 |
| 封装： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件页数： | 76/156页 |
| 文件大小： | 1701K |
| 代理商： | TLV320AIC3111IRHBT |
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SLAS644B – JULY 2009 – REVISED OCTOBER 2009
www.ti.com
5.5
Audio ADC and Analog Inputs
5.5.1
MICBIAS and Microphone Preamplifier
The TLV320AIC3111 includes a microphone bias circuit which can source up to 4 mA of current and is
programmable to a 2-V, 2.5-V, or AVDD level. The level can be controlled by writing to page 1 /
register 46, bits D1–D0. This functionality is shown in Table 5-14.
Table 5-14. MICBIAS Settings
D1
D0
FUNCTIONALITY
0
MICBIAS output is powered down.
0
1
MICBIAS output is powered to 2 V.
1
0
MICBIAS output is powered to 2.5 V.
1
MICBIAS output is powered to AVDD.
During normal operation, MICBIAS can be set to 2.5 V for better performance. However, depending on the
model of microphone that is selected, optimal performance might be obtained at another setting, so the
performance at a given setting should be verified.
The lowest current consumption occurs when MICBIAS is powered down. The next-lowest current
consumption occurs when MICBIAS is set at AVDD.
Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering,
requirements for analog anti-aliasing filtering are very relaxed. The TLV320AIC3111 integrates a
second-order analog anti-aliasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the
digital decimal filter, provides sufficient anti-aliasing filtering without requiring any external components.
The MIC PGA supports analog gain control from from 0 dB to 59.5 dB in steps of 0.5 dB. These gain
levels can be controlled by writing to page 1 / register 47, bits D6–D0. The PGA gain changes are
implemented with internal soft-stepping. This soft-stepping ensures that volume-control changes occur
smoothly with no audible artifacts. On reset, the MIC PGA gain defaults to a mute condition, with
soft-stepping enabled. The ADC soft-stepping control can be enabled or disabled by writing to page 0 /
register 81, bits D1–D0. ADC soft-stepping timing is provided by the internal oscillator and internal divider
logic block.
The input feed-forward resistance for the MIC1LP input of the microphone PGA stage has three settings,
10 k
, 20 k, and 40 k, which are controlled by writing to page 1 / register 48, bits D7 and D6. The input
feed-forward resistance value selected affects the gain of the microphone PGA. The ADC PGA gain for
the MIC1LP input depends on the setting of page1 / register 48 and page 1 / register 49, bits D7–D6. If
D7–D6 are set to 01, then the ADC PGA has 6 dB more gain with respect to the value programmed using
page 1 / register 47. If D7–D6 are set to 10, then the ADC PGA has the same gain as programmed using
page 1 / register 47. If D7–D6 are set to 11, then the ADC PGA has 6 dB less gain with respect to the
value programmed using page 1 / register 47. The same gain scaling is also valid for the MIC1RP and
MIC1LM input, based on the feed-forward resistance selected using page 1 / register 48, bits D5–D2.
The MIC PGA gain can be controlled either by an AGC loop or as a fixed gain. See Figure 1-1 for the
various analog input routings to the MIC PGA that are supported in the single-ended and differential
configurations. The AGC can be enabled by writing to page 0 / register 86, bit D7. If the AGC is not
enabled, then setting a fixed gain is done by writing to page 1 / register 47, bits D6–D0. Because the
TLV320AIC3111 supports soft-stepping gain changes, a read-only flag on page 0 / register 36, bit D7 is
set whenever the gain applied by PGA equals the desired value set by the gain register. The MIC PGA
can be enabled by writing to page 1 / register 47, bit D7. ADC muting can be done by writing to page 0 /
26
APPLICATION INFORMATION
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC3111
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