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参数资料
型号： TLV320AIC3111IRHBT
厂商： TEXAS INSTRUMENTS INC
元件分类： 音频／视频放大
英文描述： AUDIO AMPLIFIER, PQCC32
封装： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件页数： 140/156页
文件大小： 1701K
代理商： TLV320AIC3111IRHBT
TLV320AIC3111
SLAS644B – JULY 2009 – REVISED OCTOBER 2009
www.ti.com
Page 0 / Register 20: ADC AOSR_VAL(1)
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
1000 0000
0000 0000: ADC OSR AOSR divider = 256
0000 0001: ADC OSR AOSR divider = 1
0000 0010: ADC OSR AOSR divider = 2
...
1111 1110: ADC OSR AOSR divider = 254
1111 1111: ADC OSR AOSR divider = 255
(1)
ADC OSR should be an integral multiple of the decimation in the ADC miniDSP engine (specified in register 22).
Page 0 / Register 21: ADC IADC_VAL(1)
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
1000 0000
0000 0000: Reserved
0000 0001: Number of instruction for ADC miniDSP engine, IADC = 2
0000 0010: Number of instruction for ADC miniDSP engine, IADC = 4
...
1011 1111: Number of instruction for ADC miniDSP engine, IADC = 382
1100 0000: Number of instruction for ADC miniDSP engine, IADC = 384
1100 0001–1111 1111: Reserved
(1)
IADC should be an integral multiple of the decimation in the ADC miniDSP engine (specified in Register 22).
Page 0 / Register 22: ADC miniDSP Engine Decimation
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D4
R/W
0000
Reserved
D3–D0
R/W
0100
0000: Decimation ratio in ADC miniDSP engine = 16
0001: Decimation ratio in ADC miniDSP engine = 1
0010: Decimation ratio in ADC miniDSP engine = 2
...
1101: Decimation ratio in ADC miniDSP engine = 13
1110: Decimation ratio in ADC miniDSP engine = 14
1111: Decimation ratio in ADC miniDSP engine = 15
Page 0 / Register 23 and Page 0 / Register 24: Reserved
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
XXXX XXXX
Reserved. Do not write to these registers.
Page 0 / Register 25: CLKOUT MUX
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D3
R/W
0000 0
Reserved
D2–D0
R/W
000
000: CDIV_CLKIN = MCLK (device pin)
001: CDIV_CLKIN = BCLK (device pin)
010: CDIV_CLKIN = DIN (can be used for the systems where DAC is not required)
011: CDIV_CLKIN = PLL_CLK (generated on-chip)
100: CDIV_CLKIN = DAC_CLK (DAC DSP clock - generated on-chip)
101: CDIV_CLKIN = DAC_MOD_CLK (generated on-chip)
110: CDIV_CLKIN = ADC_CLK (ADC DSP clock - generated on-chip)
111: CDIV_CLKIN = ADC_MOD_CLK (generated on-chip)
84
REGISTER MAP
Copyright 2009, Texas Instruments Incorporated
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Product Folder Link(s): TLV320AIC3111
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