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参数资料
型号： TLV320AIC3111IRHBT
厂商： TEXAS INSTRUMENTS INC
元件分类： 音频／视频放大
英文描述： AUDIO AMPLIFIER, PQCC32
封装： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件页数： 128/156页
文件大小： 1701K
代理商： TLV320AIC3111IRHBT
LD(n)
LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA
-
1
-
2
-
3
2
1
0
3
-
1
-
2
-
3
2
1
0
3
-
1
-
2
N N N
-
3
RD (n)
LEFT CHANNEL
RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata
RD(n)=n'thsampleofrightchanneldata
LD(n)
LD (n+1)
WORD
CLOCK
BIT
CLOCK
DATA
-
1
4
3
2
5
1
0
-
1
4
3
2
5
1
0
N
-
1
5
RD(n)
LEFT CHANNEL
RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata
RD(n)=n'thsampleofrightchanneldata
LD(n)
LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA
-
1
-
2
-
3
2
1
0
3
-
1
-
2
-
3
2
1
0
3
-
1
-
2
N N
N
N N
N
N N
N
-
3
RD(n)
LEFT CHANNEL
RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata
RD(n)=n'thsampleofrightchanneldata
TLV320AIC3111
www.ti.com
SLAS644B – JULY 2009 – REVISED OCTOBER 2009
5.8.1.3
I2S Mode
The audio interface of the TLV320AIC3111 can be put into I2S mode by programming page 0 / register 27,
bits D7–D6 = to 00. In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit
clock after the falling edge of the word clock. Similarly, the MSB of the right channel is valid on the second
rising edge of the bit clock after the rising edge of the word clock.
Figure 5-43. Timing Diagram for I2S Mode
Figure 5-44. Timing Diagram for I2S Mode With Offset = 2
Figure 5-45. Timing Diagram for I2S Mode With Offset = 0 and Bit Clock Inverted
For I2S mode, the number of bit clocks per channel should be greater than or equal to the programmed
word length of the data. Also, the programmed offset value should be less than the number of bit clocks
per frame by at least the programmed word length of the data.
Figure 5-46 shows the timing diagram for I2S mode for the monoaural audio ADC.
Copyright 2009, Texas Instruments Incorporated
APPLICATION INFORMATION
73
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Product Folder Link(s): TLV320AIC3111
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