- 您现在的位置：买卖IC网 > PDF目录382635 > TMS320C6454ZTZ (Texas Instruments, Inc.) Fixed-Point Digital Signal Processor PDF资料下载
参数资料
| 型号： | TMS320C6454ZTZ |
| 厂商： | Texas Instruments, Inc. |
| 元件分类： | 数字信号处理 |
| 英文描述： | Fixed-Point Digital Signal Processor |
| 中文描述： | 定点数字信号处理器 |
| 文件页数： | 117/225页 |
| 文件大小： | 1663K |
| 代理商： | TMS320C6454ZTZ |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页当前第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页第189页第190页第191页第192页第193页第194页第195页第196页第197页第198页第199页第200页第201页第202页第203页第204页第205页第206页第207页第208页第209页第210页第211页第212页第213页第214页第215页第216页第217页第218页第219页第220页第221页第222页第223页第224页第225页
www.ti.com
P
7.6.2
Warm Reset (RESET Pin)
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A–APRIL 2006–REVISED DECEMBER 2006
all the system clocks are invalid at this point.
The RESETSTAT pin stays asserted (low), indicating the device is in reset.
3. The POR pin may now be deasserted (driven high).
When the POR pin is deasserted, the configuration pin values are latched and the PLL controllers
change their system clocks to their default divide-down values. PLL2 is taken out of reset and
automatically starts its locking sequence. Other device initialization is also started.
4. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). By this time,
PLL2 has already completed its locking sequence and is outputting a valid clock. The system clocks of
both PLL controllers are allowed to finish their current cycles and then paused for 10 cycles of their
respective system reference clocks. After the pause the system clocks are restarted at their default
divide-by settings.
5. The device is now out of reset, device execution begins as dictated by the selected boot mode (see
Section 2.4
,
Boot Sequence
).
NOTE
To most of the device, reset is de-asserted only when the POR and RESET pins are both
de-asserted (driven high). Therefore, in the sequence described above, if the RESET pin
is held low past the low period of the POR pin, most of the device will remain in reset. The
only exception being that PLL2 is taken out of reset as soon as POR is de-asserted
(driven high), regardless of the state of the RESET pin. The RESET pin should not be tied
together with the POR pin.
A Warm Reset has the same effects as a Power-on Reset, except that in this case, the test and emulation
logic and PLL2 are not reset.
The following sequence must be followed during a Warm Reset:
1. Hold the RESET pin low for a minimum of 24 CLKIN1 cycles. Within the minimum 24 CLKIN1 cycles.
Within the low period of the RESET pin, the following happens:
–
The Z group pins, low group pins, and the high group pins are set to their reset state with one
exception:
The PCI pins are not affected by warm reset if the PCI module was enabled before RESET went
low. In this case, PCI pins stay at whatever their value was before RESET went low.
–
The reset signals flow to the entire chip (excluding the test and emulation logic), resetting modules
that use reset asynchronously.
–
The PLL1 controller is reset thereby switching back to bypass mode and resetting all its registers to
their default values. PLL1 is placed in reset and loses lock. The PLL1 controller clocks start running
at the frequency of the system reference clock. The clocks are propagated throughout the chip to
reset modules that use reset synchronously.
–
The PLL2 controller is reset thereby resetting all its registers to their default values. The PLL2
controller clocks start running at the frequency of the system reference clock. PLL2 is not reset,
therefore it remains locked.
–
The RESETSTAT pin becomes active (low), indicating the device is in reset.
2. The RESET pin may now be released (driven inactive high).
When the RESET pin is released, the configuration pin values are latched and the PLL controllers
immediately change their system clocks to their default divide-down values. Other device initialization
is also started.
3. After device initialization is complete, the RESETSTAT pin goes inactive (high). All system clocks are
allowed to finish their current cycles and then paused for 10 cycles of their respective system reference
clocks. After the pause the system clocks are restarted at their default divide-by settings.
Submit Documentation Feedback
C64x+ Peripheral Information and Electrical Specifications
117
相关PDF资料 |
PDF描述 |
|---|---|
| TMS320C6454ZTZ7 | Fixed-Point Digital Signal Processor |
| TMS320C6454ZTZ8 | Fixed-Point Digital Signal Processor |
| TMX320C6454GTZ | Fixed-Point Digital Signal Processor |
| TMX320C6454GTZ7 | Fixed-Point Digital Signal Processor |
| TMX320C6454GTZ8 | Fixed-Point Digital Signal Processor |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TMS320C6454ZTZ7 | 制造商:TI 制造商全称:Texas Instruments 功能描述:Fixed-Point Digital Signal Processor |
| TMS320C6454ZTZ8 | 制造商:TI 制造商全称:Texas Instruments 功能描述:Fixed-Point Digital Signal Processor |
| TMS320C6455 | 制造商:TI 制造商全称:Texas Instruments 功能描述:Fixed-Point Digital Signal Processor |
| TMS320C6455_07 | 制造商:TI 制造商全称:Texas Instruments 功能描述:Fixed-Point Digital Signal Processor |
| TMS320C6455BCTZ | 功能描述:数字信号处理器和控制器 - DSP, DSC Fixed-Point Dig Sig Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
发布紧急采购，3分钟左右您将得到回复。