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| 型号： | TMX320C6203CGNZ |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 32-BIT, 300 MHz, OTHER DSP, PBGA352 |
| 封装： | PLASTIC, BGA-352 |
| 文件页数： | 12/101页 |
| 文件大小： | 1470K |
| 代理商： | TMX320C6203CGNZ |
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TMS320C6203B, TMS320C6203C
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS086G – JANUARY 1999 – REVISED JANUARY 2002
18
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
interrupt sources and interrupt selector
The C62x DSP core supports 16 prioritized interrupts, which are listed in Table 14. The highest-priority interrupt
is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The first four interrupts
(INT_00–INT_03) are non-maskable and fixed. The remaining interrupts (INT_04–INT_15) are maskable and
default to the interrupt source specified in Table 14. The interrupt source for interrupts 4–15 can be programmed
by modifying the selector value (binary value) in the corresponding fields of the Interrupt Selector Control
registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004).
Table 14. C6203B/03C DSP Interrupts
CPU
INTERRUPT
NUMBER
INTERRUPT
SELECTOR
CONTROL
REGISTER
SELECTOR
VALUE
(BINARY)
INTERRUPT
EVENT
INTERRUPT SOURCE
INT_00
–
RESET
INT_01
–
NMI
INT_02
–
Reserved
Reserved. Do not use.
INT_03
–
Reserved
Reserved. Do not use.
INT_04
MUXL[4:0]
00100
EXT_INT4
External interrupt pin 4
INT_05
MUXL[9:5]
00101
EXT_INT5
External interrupt pin 5
INT_06
MUXL[14:10]
00110
EXT_INT6
External interrupt pin 6
INT_07
MUXL[20:16]
00111
EXT_INT7
External interrupt pin 7
INT_08
MUXL[25:21]
01000
DMA_INT0
DMA channel 0 interrupt
INT_09
MUXL[30:26]
01001
DMA_INT1
DMA channel 1 interrupt
INT_10
MUXH[4:0]
00011
SD_INT
EMIF SDRAM timer interrupt
INT_11
MUXH[9:5]
01010
DMA_INT2
DMA channel 2 interrupt
INT_12
MUXH[14:10]
01011
DMA_INT3
DMA channel 3 interrupt
INT_13
MUXH[20:16]
00000
DSP_INT
Host-processor-to-DSP interrupt
INT_14
MUXH[25:21]
00001
TINT0
Timer 0 interrupt
INT_15
MUXH[30:26]
00010
TINT1
Timer 1 interrupt
–
01100
XINT0
McBSP0 transmit interrupt
–
01101
RINT0
McBSP0 receive interrupt
–
01110
XINT1
McBSP1 transmit interrupt
–
01111
RINT1
McBSP1 receive interrupt
–
10000
Reserved
Reserved. Not used.
–
10001
XINT2
McBSP2 transmit interrupt
–
10010
RINT2
McBSP2 receive interrupt
–
10011 – 11111
Reserved
Reserved. Do not use.
Interrupts INT_00 through INT_03 are non-maskable and fixed.
Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control
registers fields. Table 14 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed
information on interrupt sources and selection, see the Interrupt Selector and External Interrupts chapter of the
TMS320C6000 Peripherals Reference Guide (literature number SPRU190).
PRODUCT
PREVIEW
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