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参数资料
型号： TMX320C6203CGNZ
厂商： TEXAS INSTRUMENTS INC
元件分类： 数字信号处理
英文描述： 32-BIT, 300 MHz, OTHER DSP, PBGA352
封装： PLASTIC, BGA-352
文件页数： 17/101页
文件大小： 1470K
代理商： TMX320C6203CGNZ
TMS320C6203B, TMS320C6203C
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS086G – JANUARY 1999 – REVISED JANUARY 2002
22
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Signal Descriptions
SIGNAL
PIN NO.
SIGNAL
NAME
GNZ
GLS/
GNY
TYPE
DESCRIPTION
CLOCK/PLL
CLKIN
C12
B10
I
Clock input
CLKOUT1
AD20
Y18
O
Clock output at full device speed
CLKOUT2
AC19
AB19
O
Clock output at half (1/2) of device speed
Used for synchronous memory interface
CLKMODE0
B15
B12
I
Clock mode selects
Selects what multiply factors of the input clock frequency the CPU frequency
CLKMODE1
C11
A9
I
Selects what multiply factors of the input clock frequency the CPU frequency
equals.
For more details on the GNZ GLS and GNY CLKMODE pins and the PLL m ltipl
CLKMODE2
–
A14
I
For more details on the GNZ, GLS, and GNY CLKMODE pins and the PLL multiply
factors for the C6203B and C6203C devices, see the Clock PLL section of this data sheet.
PLLV
D13
C11
A§
PLL analog VCC connection for the low-pass filter
PLLG
D14
C12
A§
PLL analog GND connection for the low-pass filter
PLLF
C13
A11
A§
PLL low-pass filter connection to external components and a bypass capacitor
JTAG EMULATION
TMS
AD7
Y5
I
JTAG test-port mode select (features an internal pullup)
TDO
AE6
AA4
O/Z
JTAG test-port data out
TDI
AF5
Y4
I
JTAG test-port data in (features an internal pullup)
TCK
AE5
AB2
I
JTAG test-port clock
TRST
AC7
AA3
I
JTAG test-port reset (features an internal pulldown)
EMU1
AF6
AA5
I/O/Z
Emulation pin 1, pullup with a dedicated 20-k
resistor
EMU0
AC8
AB4
I/O/Z
Emulation pin 0, pullup with a dedicated 20-k
resistor
RESET AND INTERRUPTS
RESET
K2
J3
I
Device reset
NMI
L2
K2
I
Nonmaskable interrupt
Edge-driven (rising edge)
EXT_INT7
V4
U2
External interrupts
EXT_INT6
Y2
U3
I
External interrupts
Edge-driven
EXT_INT5
AA1
W1
I
Edge-driven
Polarity independently selected via the External Interrupt Polarity Register bits
(EXTPOL [3 0])
EXT_INT4
W4
V2
yy
y
g
(EXTPOL.[3:0])
IACK
Y1
V1
O
Interrupt acknowledge for all active interrupts serviced by the CPU
INUM3
V2
R3
INUM2
U4
T1
O
Active interrupt identification number
Valid during IACK for all active interrupts (not just external)
INUM1
V3
T2
O
Valid during IACK for all active interrupts (not just external)
Encoding order follows the interrupt-service fetch-packet ordering
INUM0
W2
T3
Encoding order follows the interru t-service fetch- acket ordering
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
PLLV, PLLG, and PLLF are not part of external voltage supply or ground. See the clock PLL section for information on how to connect these pins.
§ A = Analog Signal (PLL Filter)
For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-k
resistor. For boundary scan, pull down EMU1 and EMU0
with a dedicated 20-k
resistor.
PRODUCT
PREVIEW
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