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参数资料
| 型号： | TMX320C6203CGNZ |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 32-BIT, 300 MHz, OTHER DSP, PBGA352 |
| 封装： | PLASTIC, BGA-352 |
| 文件页数： | 33/101页 |
| 文件大小： | 1470K |
| 代理商： | TMX320C6203CGNZ |
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TMS320C6203B, TMS320C6203C
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS086G – JANUARY 1999 – REVISED JANUARY 2002
37
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
clock PLL
Most of the internal C6203B/03C clocks are generated from a single source through the CLKIN pin. This source
clock either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock,
or bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 5,
and Table 17 through Table 19 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply
modes. Figure 6 shows the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode.
To minimize the clock jitter, a single clean power supply should power both the C6203B/03C device and the
external clock oscillator circuit. Noise coupling into PLLF directly impacts PLL clock jitter. The minimum CLKIN
rise and fall times should also be observed. For the input clock timing requirements, see the input and output
clocks electricals section. Table 16 lists some examples of compatible CLKIN external clock sources:
Table 16. Compatible CLKIN External Clock Sources
COMPATIBLE PARTS FOR
EXTERNAL CLOCK SOURCES (CLKIN)
PART NUMBER
MANUFACTURER
JITO-2
Fox Electronix
Oscillators
STA series, ST4100 series
SaRonix Corporation
Oscillators
SG-636
Epson America
342
Corning Frequency Control
PLL
MK1711-S, ICS525-02
Integrated Circuit Systems
CLKMODE0
CLKMODE1
PLL
PLLV
CLKIN
LOOP FILTER
PLLCLK
PLLMULT
CLKIN
PLLG
C2
Internal to
C6203B/C6203C
CPU
CLOCK
C1
R1
3.3V
10
mF
0.1
mF
PLLF
C3
C4
1
0
CLKMODE2
(For the PLL Options
and CLKMODE pins setup,
see Table 17 through Table 20)
The CLKMODE2 pin is not available for the C6203C GNZ package.
EMI Filter
NOTES: A. Keep the lead length and the number of vias between pin PLLF, pin PLLG, R1, C1, and C2 to a minimum. In addition, place all PLL
components (R1, C1, C2, C3, C4, and EMI Filter) as close to the C6000
DSP device as possible. Best performance is achieved
with the PLL components on a single side of the board without jumpers, switches, or components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4,
and the EMI Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
D. EMI filter manufacturer: TDK part number ACF451832-333, 223, 153, 103. Panasonic part number EXCCET103U.
Figure 5. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode
PRODUCT
PREVIEW
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