
TMS320C6203B, TMS320C6203C
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS086G – JANUARY 1999 – REVISED JANUARY 2002
2
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Table of Contents
signal transition levels
42
. . . . . . . . . . . . . . . . . . . . . . . . . .
timing parameters and board routing analysis
43
. . . . . .
input and output clocks
44
. . . . . . . . . . . . . . . . . . . . . . . . . . .
asynchronous memory timing
47
. . . . . . . . . . . . . . . . . . . . .
synchronous-burst memory timing
51
. . . . . . . . . . . . . . . . .
synchronous DRAM timing
56
. . . . . . . . . . . . . . . . . . . . . . . .
HOLD/HOLDA timing
63
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
reset timing
64
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
external interrupt timing
66
. . . . . . . . . . . . . . . . . . . . . . . . . .
expansion bus synchronous FIFO timing
67
. . . . . . . . . . . .
expansion bus asynchronous peripheral timing
69
. . . . . .
expansion bus synchronous host-port timing
73
. . . . . . . .
expansion bus asynchronous host-port timing
79
. . . . . . .
XHOLD/XHOLDA timing
81
. . . . . . . . . . . . . . . . . . . . . . . . . .
multichannel buffered serial port timing
83
. . . . . . . . . . . . .
DMAC, timer, power-down timing
95
. . . . . . . . . . . . . . . . . .
JTAG test-port timing
97
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
mechanical data
98
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GNZ, GLS, and GNY BGA packages (bottom view)
2
. . . .
description
4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
device characteristics
4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C62x device compatibility
7
. . . . . . . . . . . . . . . . . . . . . . . . . . .
functional and CPU (DSP core) block diagram
8
. . . . . . . . .
CPU (DSP core) description
9
. . . . . . . . . . . . . . . . . . . . . . . .
memory map summary
11
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
peripheral register descriptions
12
. . . . . . . . . . . . . . . . . . . . .
DMA synchronization events
17
. . . . . . . . . . . . . . . . . . . . . . .
interrupt sources and interrupt selector
18
. . . . . . . . . . . . . .
signal groups description
19
. . . . . . . . . . . . . . . . . . . . . . . . . .
signal descriptions
22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
development support
33
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
documentation support
36
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
clock PLL
37
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
power-supply sequencing
40
. . . . . . . . . . . . . . . . . . . . . . . . . .
absolute maximum ratings over operating case
temperature ranges
41
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions
41
. . . . . . . . . . . . . . . . .
electrical characteristics over recommended ranges
of supply voltage and operating case temperature
41
. .
parameter measurement information
42
. . . . . . . . . . . . . . . .
GNZ, GLS, and GNY BGA packages (bottom view)
GNZ 352-PIN BALL GRID ARRAY (BGA) PACKAGE (BOTTOM VIEW) [C6203C only]
AF
AD
AB
AA
AC
W
Y
U
V
AE
R
N
P
L
H
J
K
M
F
G
D
E
B
A
C
T
25
26
22
23
20
19
21
17
15
16
12
13
14
18
10
9
8
7
5
6
4
3
2
111
24
PRODUCT
PREVIEW