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参数资料
| 型号： | TMX320C6203CGNZ |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 32-BIT, 300 MHz, OTHER DSP, PBGA352 |
| 封装： | PLASTIC, BGA-352 |
| 文件页数： | 19/101页 |
| 文件大小： | 1470K |
| 代理商： | TMX320C6203CGNZ |
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TMS320C6203B, TMS320C6203C
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS086G – JANUARY 1999 – REVISED JANUARY 2002
24
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Signal Descriptions (Continued)
SIGNAL
PIN NO.
SIGNAL
NAME
GNZ
GLS/
GNY
TYPE
DESCRIPTION
EXPANSION BUS (CONTINUED)
XCE3
F2
D2
XCE2
E1
B1
O/Z
Expansion bus I/O port memory space enables
Enabled by bits 28 29 and 30 of the word address
XCE1
F3
D3
O/Z
Enabled by bits 28, 29, and 30 of the word address
Only one asserted during any I/O port data access
XCE0
E2
C2
Only one asserted during any I/O ort data access
XBE3/XA5
C7
C5
XBE2/XA4
D8
A4
I/O/Z
Expansion bus multiplexed byte-enable control/address signals
Act as byte enable for host port operation
XBE1/XA3
A6
B5
I/O/Z
Act as byte-enable for host-port operation
Act as address for I/O port operation
XBE0/XA2
C8
C6
Act as address for I/O ort o eration
XOE
A7
A6
O/Z
Expansion bus I/O port output-enable
XRE
C9
C7
O/Z
Expansion bus I/O port read-enable
XWE/XWAIT
D10
B7
O/Z
Expansion bus I/O port write-enable and host-port wait signals
XCS
A10
C9
I
Expansion bus host-port chip-select input
XAS
D9
B6
I/O/Z
Expansion bus host-port address strobe
XCNTL
B10
B9
I
Expansion bus host control. XCNTL selects between expansion bus address or data register.
XW/R
D11
B8
I/O/Z
Expansion bus host-port write/read-enable. XW/R polarity is selected at reset.
XRDY
A5
C4
I/O/Z
Expansion bus host-port ready (active low) and I/O port ready (active high)
XBLAST
B6
B4
I/O/Z
Expansion bus host-port burst last-polarity selected at reset
XBOFF
B11
A10
I
Expansion bus back off
XHOLD
B5
A2
I/O/Z
Expansion bus hold request
XHOLDA
D7
B3
I/O/Z
Expansion bus hold acknowledge
EMIF – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
CE3
AB25
Y21
CE2
AA24
W20
O/Z
Memory space enables
Enabled by bits 24 and 25 of the word address
CE1
AB26
AA22
O/Z
Enabled by bits 24 and 25 of the word address
Only one asserted during any external data access
CE0
AA25
W21
Only one asserted during any external data access
BE3
Y24
V20
Byte-enable control
BE2
W23
V21
O/Z
Byte-enable control
Decoded from the two lowest bits of the internal address
BE1
AA26
W22
O/Z
Decoded from the two lowest bits of the internal address
Byte-write enables for most types of memory
C
b di
tl
t d t SDRAM
d
it
k i
l (SDQM)
BE0
Y25
U20
yy
y
Can be directly connected to SDRAM read and write mask signal (SDQM)
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
PRODUCT
PREVIEW
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| TMX320C6203GGP100 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR |
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| TMX320C6203GLS | 制造商:Texas Instruments 功能描述: |
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