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| 型号： | TZA3015HW |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 数字传输电路 |
| 英文描述： | 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver |
| 中文描述： | TRANSCEIVER, PQFP100 |
| 封装： | 14 X 14 MM, 1 MM HEIGHT, SOT-638-1, HTQFP-100 |
| 文件页数： | 19/67页 |
| 文件大小： | 352K |
| 代理商： | TZA3015HW |
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2003 Dec 16
19
Philips Semiconductors
Preliminary specification
30 Mbit/s to 3.2 Gbit/s A-rate
4-bit fibre optic transceiver
TZA3015HW
Transmitter
C
LOCK SYNTHESIZER
The transmitter frequency can be set independently of the
receiverfrequency.Forthisaclocksynthesizerisprovided
that drives the multiplexer. Just like the DCR the clock
synthesizer is built around a fractional N synthesizer
offering A-rate functionality for the transmit path.
The clock synthesizer consists of a VCO, several dividers,
aphasefrequencydetector,anintegrated loopfilter,alock
detection circuit and a prescaler output buffer (see Fig.14).
The internal VCO is phase-locked to the reference clock
signal provided at pins CREF(Q). This frequency is
internally scaled down (if necessary) to a frequency in the
range of 18 to 21 MHz by divider R.
Because of the 22 bits fractional N capability, any
combination of bit rate (30 Mbit/s to 3.2 Gbit/s) and
referencefrequencybetween18 and672 MHzispossible.
The LSB (bit k0) of the fractional divider, should be set to
logic 1 to avoid limit cycles. These are cycles of less than
maximum length, which generate spurs in the frequency
spectrum. This leaves bits k[21:1] available for
programmingthefraction,allowingapproximately10 Hzof
frequency resolution without altering the reference
frequency.
To meet most transmission standards, the reference
frequency should be very accurate. In order to be able to
synthesize a clean RF clock that is compliant with the most
stringent jitter generation requirements, it should also be
very clean in terms of phase noise.
handbook, full pagewidth
MGU682
÷
N
CHARGE PUMP
AND
LOOP FILTER
MAIN
DIVIDER N, K
OCTAVE
DIVIDER
divided
CREF(Q)
TXPRSCL(Q)
VCO
to LM MUX
and
multiplexer
PHASE
FREQUENCY
DETECTOR
up
LOL
down
÷
M
Fig.14 Schematic diagram of the clock synthesizer.
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| TZA3017HW | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:30 Mbits/s up to 3.2 Gbits/s A-rate fibre optic transmitter |
| TZA3019 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch |
| TZA3019AHT | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch |
| TZA3019AV | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch |
| TZA3019AVH | 制造商:未知厂家 制造商全称:未知厂家 功能描述:APPLICATION SPECIFIC AMPLIFIER|DUAL|LLCC|32PIN|PLASTIC |
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