参数资料
型号: TZA3015HW
厂商: NXP SEMICONDUCTORS
元件分类: 数字传输电路
英文描述: 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver
中文描述: TRANSCEIVER, PQFP100
封装: 14 X 14 MM, 1 MM HEIGHT, SOT-638-1, HTQFP-100
文件页数: 30/67页
文件大小: 352K
代理商: TZA3015HW
2003 Dec 16
30
Philips Semiconductors
Preliminary specification
30 Mbit/s to 3.2 Gbit/s A-rate
4-bit fibre optic transceiver
TZA3015HW
A
CKNOWLEDGE
Figure 23 shows the definition of an acknowledgement on
the I
2
C-bus. Only one data byte is transferred between the
startandstopconditionsduringawritefromthetransmitter
to the receiver. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock
pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter.
The device that acknowledges must pull down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal an end of data to the transmitter by
not
generating
an acknowledge on the
last byte
that has been clocked
outoftheslave.Inthiseventthetransmittermustleavethe
data line HIGH to enable the master to generate a stop
condition.
handbook, full pagewidth
MBC622
SDA
SCL
P
STOP condition
SDA
SCL
S
START condition
Fig.22 Start and stop conditions.
handbook, full pagewidth
MBC602
S
START
condition
9
8
2
1
clock pulse for
acknowledgement
not acknowledge
acknowledge
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
Fig.23 (Not) acknowledge condition on the I
2
C-bus.
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