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| 型号： | TZA3015HW |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 数字传输电路 |
| 英文描述： | 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver |
| 中文描述： | TRANSCEIVER, PQFP100 |
| 封装： | 14 X 14 MM, 1 MM HEIGHT, SOT-638-1, HTQFP-100 |
| 文件页数： | 22/67页 |
| 文件大小： | 352K |
| 代理商： | TZA3015HW |
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2003 Dec 16
22
Philips Semiconductors
Preliminary specification
30 Mbit/s to 3.2 Gbit/s A-rate
4-bit fibre optic transceiver
TZA3015HW
Double data rate mode
Usually the parallel clock frequency (TXPC, RXPC and
TXPCO) equals the parallel data rate (for example when
the serial bit rate is 2.488 Gbit/s, the parallel bit rate is
622 Mbit/s and the data is clocked with a 622 MHz clock).
This is the default operating mode.
However, in some applications it is required to use a
parallel clock operating at a frequency that is half of the
parallel data rate. This is the DDR mode (for example
when the serial bit rate is 2.488 Gbit/s, the parallel bit rate
is 622 Mbit/s and the data is clocked at both the rising as
well as the falling edge of the 311 MHz clock). The timing
for the parallel input interface is in accordance with the
SFI4 specification.
The DDR functionality can be enabled by pin ENDDR (see
Table 12) or via the I
2
C-bus. I
2
C-bus control is enabled by
setting bit I2CDDR of register DDR&RXPRSCL (D5h).
In I
2
C-bus mode the three parallel clocks can be set
separately in the DDR mode by bits RXPCDDREN,
TXPCDDREN and TXPCODDREN of registers
DDR&RXPRSCL (D5h), MUXCON0 (F1h) and
TXMFOUTC (F2h) respectively (see Tables 13, 14 and
15).
The DDR mode is functional for the whole bit-rate range,
so it is true A-rate.
Table 12
Truth table for pin ENDDR
Table 13
Truth table for bit RXPCDDREN
Table 14
Truth table for bit TXPCDDREN
Table 15
Truth table for bit TXPCODDREN
FIFO register
In the co-directional clocking scheme, the input register
samples the parallel bus data on the rising edge of the
clock signal TXPC(Q). The same clock writes this data into
the FIFO register. Data is retrieved from the FIFO by an
internal clock, derived from the clock generator of the
actual multiplexing tree. This provides for large jitter
tolerance on the parallel interface; the FIFO absorbs
momentary phase disturbances. Excessively large phase
disturbances may stretch the elastic buffer to its limits,
causing a FIFO overflow or underflow. Pin OVERFLOW
and the registers STATUS (01h) and INTERRUPT (00h)
indicate this situation. On demand (i.e to programmed in
the register INTMASK [A0h]) it generates an interrupt
signal at pin INT.
The overflow alarm persists until the FIFO is reset by a
HIGH-level on pin FIFORESET or by setting bit
FIFORESET of register MUXCON0 (F1h) to logic 1.
A FIFORESET also initializes the FIFO. I
2
C-bus control of
the FIFORESET function is obtained by programming bit
I2CFIFORES of register MUXCON0 (F1h). To fully benefit
from the FIFO, it should be reset whenever there has been
a LOL condition, or when bit rates have changed.
The asynchronous signal FIFORESET is re-timed by the
internal clock from the clock generator. Two clock cycles
after signal FIFORESET has been made HIGH, the FIFO
initializes. Two clock cycles after signal FIFORESET has
been made LOW, the FIFO will be operational again.
To initializeautomatically,whenanoverflowhasoccurred,
it is possible to connect pin OVERFLOW to pin
FIFORESET directly or via a resistor.
Multiplexing bus swap
Bit TXBUSSWAP of register MUXCON1 (F0h) swaps the
bus order of the parallel data input bus TXPD0(Q) to
TXPD3(Q). Bit TXBUSSWAP reverses the order of bits
from MSB to LSB, or vice versa, to allow for optimum
connectivity on the PCB.
ENDDR
MODE
LOW
TXPC, RXPC and TXPCO in normal
mode
TXPC, RXPC and TXPCO in DDR
mode
HIGH
RXPCDDREN
MODE
1
0
RXPC in DDR mode
RXPC in normal mode
TXPCDDREN
MODE
1
0
TXPC in DDR mode
TXPC in normal mode
TXPCODDREN
MODE
1
0
TXPCO in DDR mode
TXPCO in normal mode
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