参数资料
型号: TZA3015HW
厂商: NXP SEMICONDUCTORS
元件分类: 数字传输电路
英文描述: 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver
中文描述: TRANSCEIVER, PQFP100
封装: 14 X 14 MM, 1 MM HEIGHT, SOT-638-1, HTQFP-100
文件页数: 44/67页
文件大小: 352K
代理商: TZA3015HW
2003 Dec 16
44
Philips Semiconductors
Preliminary specification
30 Mbit/s to 3.2 Gbit/s A-rate
4-bit fibre optic transceiver
TZA3015HW
Table 52
Register TXFRACN2 (address: E3h, default value: 80h)
Table 53
Register TXFRACN1 (address: E4h, default value: 00h)
Table 54
Register TXFRACN0 (address: E5h, default value: 00h)
Table 55
Register MUXCON1 (address: F0h, default value: 62h)
BIT
PARAMETER
7
6
5
4
3
2
1
0
DESCRIPTION
NAME
x
x
x
x
x
x
fractional divider: TXK21 = MSB
TXK[21:16]
reserved
TXNILFRAC
x
TXNILFRAC control bit (NF)
no fractional N functionality
fractional N functionality
1
0
1
0
0
0
0
0
0
0
default value
BIT
PARAMETER
7
6
5
4
3
2
1
0
DESCRIPTION
NAME
x
0
x
0
x
0
x
0
x
0
x
0
x
0
x
0
fractional divider
TXK[15:8]
default value
BIT
PARAMETER
7
6
5
4
3
2
1
0
DESCRIPTION
NAME
x
0
x
0
x
0
x
0
x
0
x
0
x
0
x
0
fractional divider; TXK0 = LSB
TXK[7:0]
default value
BIT
PARAMETER
7
6
5
4
3
2
1
0
DESCRIPTION
NAME
parallel INPUT bus swapping
TXPD0 = MSB; TXPD3 = LSB (swapped)
TXPD3 = MSB; TXPD0 = LSB (normal)
parity polarity
even parity
odd parity
parity programming by I
2
C-bus
by I
2
C-bus interface
by external pin PAREVEN
parallel clock input polarity
inverted
normal
TXBUSSWAP
1
0
TXPAREVEN
1
0
I2CTXPAREVEN
1
0
TXPCINV
1
0
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