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参数资料
型号： TZA3015HW
厂商： NXP SEMICONDUCTORS
元件分类： 数字传输电路
英文描述： 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver
中文描述： TRANSCEIVER, PQFP100
封装： 14 X 14 MM, 1 MM HEIGHT, SOT-638-1, HTQFP-100
文件页数： 32/67页
文件大小： 352K
代理商： TZA3015HW
2003 Dec 16
32
Philips Semiconductors
Preliminary specification
30 Mbit/s to 3.2 Gbit/s A-rate
4-bit fibre optic transceiver
TZA3015HW
I
2
C-BUS REGISTERS
The TZA3015HW can be programmed via the I
2
C-bus if pin UI = HIGH or leaving the pin open-circuit. The I
2
C-bus
registers can be accessed via the 2-wire I
2
C-bus interface using pins SCL and SDA if pin CS = HIGH during read or write
actions. The I
2
C-bus address of the TZA3015HW can be found in Table 2.
Table 21
I
2
C-bus registers
ADDRESS
(HEX)
NAME
FUNCTION
DEFAULT
RANGE
R/W
General part
00
01
A0
A1
INTERRUPT
STATUS
INTMASK
REFDIV
interrupt register (see Table 22)
status register (see Table 23)
interrupt mask register (see Table 24)
reference divider and clean-up PLL
(see Table 25)
loop mode and enable register (see Table 26)
LVDS output buffer configuration (see Table 27)
interrupt output configuration (see Table 28)
XXXX XXXX
XXXX XXXX
0000 0100
0000 0000
n.a.
n.a.
n.a.
n.a.
R
R
W
W
A3
A4
A5
LOOPMODE
MFOBCON
INTCONF
0110 0111
0101 0000
0000 0001
n.a.
n.a.
n.a.
W
W
W
Transceiver
B0
B1
B2
B3
B4
HEADER3
HEADER2
HEADER1
HEADER0
HEADERX3
programmable header; MSB (see Table 29)
programmable header (see Table 30)
programmable header (see Table 31)
programmable header; LSB (see Table 32)
programmable header don’t care; MSB
(see Table 33)
programmable header don’t care (see Table 34)
programmable header don’t care (see Table 35)
programmable header don’t care; LSB
(see Table 36)
demultiplexer configuration register
(see Table 37)
DCR octave M divider (see Table 38)
VCO frequency N divider (see Table 39)
VCO frequency N divider (see Table 40)
fractional division (see Table 41)
fractional division (see Table 42)
fractional division (see Table 43)
DCR configuration register (see Table 44)
limiter loss threshold
limiter loss of signal configuration register
(see Table 45)
limiter slice level
limiter amplifier configuration (see Table 46)
disable/invert parallel outputs (see Table 47)
1111 0110
1111 0110
0010 1000
0010 1000
0000 0000
n.a.
n.a.
n.a.
n.a.
n.a.
W
W
W
W
W
B5
B6
B7
HEADERX2
HEADERX1
HEADERX0
0000 0000
0000 0000
0000 0000
n.a.
n.a.
n.a.
W
W
W
B8
DMXCON
0000 0000
n.a.
W
C0
C1
C2
C3
C4
C5
C6
D0
D1
RXOCTDIV
RXMAINDIV1
RXMAINDIV0
RXFRACN2
RXFRACN1
RXFRACN0
DCRCON
LIMLOSTH
LIMLOSCON
0000 0000
0000 0001
0000 0000
1000 0000
0000 0000
0000 0000
0000 1100
0000 0000
0000 1101
n.a.
128 to 511
128 to 511
n.a.
n.a.
n.a.
n.a.
0 to 255
n.a.
W
W
W
W
W
W
W
W
W
D2
D3
D4
LIMSL
LIMCON
RXMFOUTC0
0000 0000
0000 0000
1010 1010
0 to 255
n.a.
n.a.
W
W
W
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