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参数资料
| 型号： | TZA3015HW |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 数字传输电路 |
| 英文描述： | 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver |
| 中文描述： | TRANSCEIVER, PQFP100 |
| 封装： | 14 X 14 MM, 1 MM HEIGHT, SOT-638-1, HTQFP-100 |
| 文件页数： | 27/67页 |
| 文件大小： | 352K |
| 代理商： | TZA3015HW |
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2003 Dec 16
27
Philips Semiconductors
Preliminary specification
30 Mbit/s to 3.2 Gbit/s A-rate
4-bit fibre optic transceiver
TZA3015HW
Parallel clock output
Bit RXPCINV of register RXMFOUTC0 (D4h) sets the
polarity of the parallel clock output RXPC(Q), effectively
shifting the clock edge by half a clock cycle and changing
the rising edge to a falling edge. This might resolve a
parallel bus timing problem. The parallel clock output can
be disabled by programming bit RXPCEN of register
RXMFOUTC0 (D4h).
Parallel data output
The parallel output bus data RXPD0(Q) to RXPD3(Q) can
be swapped by bit RXBUSSWAP of register DMXCON
(B8h). The mute option forces the parallel output bits to a
logic 0 state. This is done by programming bit DMXMUTE
of register DMXCON (B8h). The polarity of the data
RXPD0(Q) to RXPD3(Q) can be set by bit RXPDINV of
register RXMFOUTC0 (D4h). The data outputs can be
disabled by programming bit RXPDEN of register
RXMFOUTC0 (D4h).
Frame pulse output
The polarity of the frame pulse output RXFP(Q) is set by
bit RXFPINV of register RXMFOUTC0 (D4h). The frame
pulse output can be disabled by programming bit RXFPEN
of register RXMFOUTC0 (D4h).
Parity output
The polarity of the parity output RXPAR(Q) is set by bit
RXPARINV of register RXMFOUTC0 (D4h). The parity
output can be disabled by programming bit RXPAREN of
register RXMFOUTC0 (D4h).
Parity error output
The polarity of the parity error output TXPARERR(Q) is set
by bit TXPARERRINV of register TXMFOUTC (F2h). The
parity error output can be disabled by programming bit
TXPARERREN of register TXMFOUTC (F2h).
Transmitter parallel clock output
Bit TXPCOINV of register TXMFOUTC (F2h) sets the
polarity of the parallel clock output TXPCO(Q), effectively
shifting the clock edge by half a clock cycle and changing
the rising edge to a falling edge. The phase of the clock
can be shifted by 90
°
by programming bit TXPCOPHASE
ofregisterMUXCON0(F1h).Thecombinationofthesetwo
bits offers a phase shift range of 0 to 360
°
, adjustable in
four steps (step size 90
°
). This might resolve a parallel bus
timing problem. The parallel clock output can be disabled
by programming bit TXPCOEN of register TXMFOUTC
(F2h).
Prescaler DCR output
The polarity of the receiver prescaler output RXPRSCL(Q)
is set by bit RXPRSCLINV of register DDR&RXPRSCL
(D5h). The receiver prescaler output can be disabled by
programming bit RXPRSCLEN of register
DDR&RXPRSCL (D5h).
Prescaler synthesizer output
The polarity of the transmitter prescaler output
TXPRSCL(Q) is set by bit TXPRSCLINV of register
TXMFOUTC (F2h). The transmitter prescaler output can
be disabled by programming bit TXPRSCLEN of register
TXMFOUTC (F2h).
LVDS
INPUTS
The available LVDS inputs are:
Parallel clock input; pins TXPC(Q)
Parallel data input; pins TXPD0(Q) to TXPD3(Q)
Parity input; pins TXPAR(Q).
The differential LVDS inputs can handle any input swing
with a minimum of 100 mV (p-p) single-ended. The inputs
accept any value between V
EE
and V
CC
, i.e. the input
buffers are true rail-to-rail. The limiting value of the LVDS
input current is 25 mA. A differential hysteresis of 25 mV is
implemented; see Fig.33.
Parallel clock input
Bit TXPCINV of register MUXCON1 (F0h) sets the polarity
of the parallel clock input TXPC(Q), effectively shifting the
clock edge by half a clock cycle and changing the rising
edge to a falling edge. This could be used to resolve a
parallel bus timing problem.
Parallel data input
The order of the parallel output bus data TXPD0(Q) to
TXPD3(Q) can be programmed by bit TXBUSSWAP of
register MUXCON1 (F0h).
Bit TXPDINV of register MUXCON1 (F0h) sets the polarity
of the parallel data inputs TXPD0(Q) to TXPD3(Q).
RF
OUTPUTS
The serial RF outputs are CML type outputs (see Figs 31
and 32). Several options exist that allow flexible
configuration of the RF outputs: output amplitude
adjustment, signal polarity, data-clock swap, output
termination and selective enable/disable of the clock
output. Thus, the TZA3015HW can be configured so that
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| TZA3017HW | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:30 Mbits/s up to 3.2 Gbits/s A-rate fibre optic transmitter |
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