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| 型号： | TZA3015HW |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 数字传输电路 |
| 英文描述： | 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver |
| 中文描述： | TRANSCEIVER, PQFP100 |
| 封装： | 14 X 14 MM, 1 MM HEIGHT, SOT-638-1, HTQFP-100 |
| 文件页数： | 25/67页 |
| 文件大小： | 352K |
| 代理商： | TZA3015HW |
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2003 Dec 16
25
Philips Semiconductors
Preliminary specification
30 Mbit/s to 3.2 Gbit/s A-rate
4-bit fibre optic transceiver
TZA3015HW
handbook, full pagewidth
MCE418
4
4
4
4
4
SYNTHESIZER
MULTIPLEXER
parallel
data
parallel
clock
parallel
data
parallel
clock
serial
data
serial
data
serial
clock
DEMULTIPLEXER
DCR
LIMITER
data
clock
data
clock
Fig.19 Serial loop timing mode.
Clean-up loop back mode
The TZA3015HW can be used in transponder
applications. In this application, the transmitter is locked
onto the recovered clock from the DCR (RXPRSCL).
Withoutpreparations,thejittertransferofthisapplicationis
determinedbycascadingthetransferfunctionsoftheDCR
and the clock synthesizer. This transfer function is not well
controlled and may not meet the required specification in
terms of bandwidth and/or jitter peaking. A second
drawback is that the jitter generation of the synthesizer is
degraded because the frequency reference (i.e. the DCR)
is not very clean in terms of phase-noise.
To improve both the jitter transfer and jitter generation in
transponder applications, an external low-noise reference
oscillator is locked onto the DCR recovered clock by
means of a small band PLL, i.e. the clean-up PLL. The
low-noise oscillator, e.g. a Voltage Controlled Crystal
Oscillator (VCXO), acts as the reference for the clock
synthesizer. If appropriately designed, the jitter will be
dominated by the clean-up PLL. This PLL can be
optimized for bandwidth and jitter peaking, while the jitter
generation is optimized by choosing the appropriate
VCXO.
Figure 20 shows a typical clean-up PLL application. For
ease of use, all components are integrated in the
TZA3015HW, except for the VCXO and the loop filter
components. The PLL consists of a phase frequency
detector, a charge pump, an external loop filter (R, C1 and
C2), a VCXO and a reference divider. The combination of
RandC1ismandatoryand willtransformthecurrentatthe
output of the charge pump into a control voltage for the
VXCO. Capacitor C2 is optional.
The internal clock and data path in the TZA3015HW is
clarified in Fig.21. As can be seen in the clean-up
application, the received (and transmitted) data is also
available in parallel format at the parallel output bus.
Two bits are available to ease the design of the clean-up
PLL. The loop is designed to work with a VCXO that has a
positive gain. That is an increasing voltage on the VCXO
control input will increase the output frequency. By means
of bit CLUPPLLINV of register REFDIV (A1h) the loop is
inverted and will work with VCXOs which have a negative
gain. Bit CLUPPLLHG of register REFDIV (A1h) will
change the gain of the charge pump. If bit CLUPPLLHG is
logic 0, the charge pump current I
CP
is 100
μ
A. If bit
CLUPPLLHG is logic 1, the charge pump current I
CP
is
1 mA. This eases choosing suitable component values for
R and C1.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TZA3017HW | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:30 Mbits/s up to 3.2 Gbits/s A-rate fibre optic transmitter |
| TZA3019 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch |
| TZA3019AHT | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch |
| TZA3019AV | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch |
| TZA3019AVH | 制造商:未知厂家 制造商全称:未知厂家 功能描述:APPLICATION SPECIFIC AMPLIFIER|DUAL|LLCC|32PIN|PLASTIC |
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