- 您现在的位置：买卖IC网 > PDF目录373750 > TZA3015HW (NXP SEMICONDUCTORS) 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver PDF资料下载
参数资料
| 型号： | TZA3015HW |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 数字传输电路 |
| 英文描述： | 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver |
| 中文描述： | TRANSCEIVER, PQFP100 |
| 封装： | 14 X 14 MM, 1 MM HEIGHT, SOT-638-1, HTQFP-100 |
| 文件页数： | 29/67页 |
| 文件大小： | 352K |
| 代理商： | TZA3015HW |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页当前第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页
2003 Dec 16
29
Philips Semiconductors
Preliminary specification
30 Mbit/s to 3.2 Gbit/s A-rate
4-bit fibre optic transceiver
TZA3015HW
The CMOS inputs have an internal pull-up resistance; if
the input is left open, a logic HIGH state will be forced
internally. In the pre-programmed mode (UI = LOW), pins
DR0 to 2 act as regular CMOS inputs. In the I
2
C-bus mode
(UI = HIGH), pins SCL and SDA comply with the I
2
C-bus
interface standard.
O
PEN
-
DRAIN OUTPUT
TheTZA3015HWcontainsoneopen-draininterruptoutput
pin INT. The output type of the interrupt controller can be
configured by programming bit INTOUT of register
INTCONF (A5h). The output can be configured as a
push-pullCMOSoutputorasanopen-drainoutput.Forthe
open-drain configuration an external pull-up resistor of
3.3 k
is recommended. The polarity can be set by
programming bit INTPOL of register INTCONF (A5h).
I
NTERRUPT GENERATION
The TZA3015HW features a fully configurable interrupt
generator. An interrupt signal can be generated in the
following events:
Loss Of Signal (LOS)
INWINDOW
Temperature alarm
Loss Of Lock (LOL)
FIFO overflow or underflow.
The aforementioned events generate flags which can be
read in register STATUS (01h). Each of these flags will
generate an interrupt in the INTERRUPT register (00h).
If programmed so in the register INTMASK (A0h) the
INTERRUPT register bit(s) will generate an interrupt on
pin INT. In this mask register each interrupt bit can be
masked by writing a logic 0 in the corresponding bit
position.
The STATUS register shows the present status of the
receiver. The INTERRUPT register shows the history of
the interrupts and is not affected by the INTMASK register.
Bit INTOUT of register INTCONF (A5h) determines the
output type of pin INT: standard CMOS output or
open-drain output. The latter is the default which provides
for multiple receivers sharing a common interrupt signal
wire with a 3.3 k
pull-up resistor (INT is active LOW in
this case). The polarity can be set by programming bit
INTPOL of register INTCONF (A5h).
The interrupt and status register can be polled by an
I
2
C-bus read action. After the read action on the interrupt
register the interrupt register is reset by clearing the
interrupt bits where the ‘alarm’ is no longer present. If the
‘alarm’ is still set, the interrupt bit is not cleared after the
read action. If an interrupt bit remains set (and if it is not
masked) the INT pin will keep its interrupt condition active;
it will not generate a pulse nor a spike. The I
2
C-bus status
register is not reset since it always shows the present
status of the receiver. It is important to note that the three
reserved bits of the STATUS and INTERRUPT registers
can take any value and that they can change during
operating.Thesebitscannotbeusedtoobtaininformation
on the status of the IC.
Power supply connections
Four separate supply domains (V
DD
, V
CCD
, V
CCO
and
V
CCA
) provide isolation between the various functional
blocks. Each supply domain should be connected to a
common V
CC
via separate filters. All supply domains
should be powered synchronously.
All supply pins, including the exposed die pad, must be
connected. The die pad should be connected with the
lowest inductance possible. Since the die pad is also used
as the main ground return of the chip, the connection
should have a low DC impedance as well. The voltage
supply levels should be in accordance with the values
specified in Chapter “Characteristics”.
All external components should be surface mounted
devices, preferably of size 0603 or smaller. The
components must be mounted as closely to the IC as
possible.
I
2
C-BUS
I
2
C-bus characteristics
The I
2
C-bus is a 2-line communication between different
ICs or modules. The two lines are a serial data line (SDA)
and a serial clock line (SCL). Data transfer may be initiated
only when the line is not busy.
S
TART AND STOP CONDITIONS
Figure 22 shows the definition of the start and stop
conditions. Both data and clock lines remain HIGH when
the bus is not busy. A HIGH-to-LOW transition of the data
line, while the clock is HIGH is defined as the start
condition (S). A LOW-to-HIGH transition of the data line
while the clock is HIGH is defined as the stop condition (P).
相关PDF资料 |
PDF描述 |
|---|---|
| Z00607DA | SENSITIVE GATE TRIACS |
| Z00607DA1BA2 | SENSITIVE GATE TRIACS |
| Z00607MA | Fuses, 20A 250V CERAMIC |
| Z0100A | surface mount silicon Zener diodes |
| Z0110A | surface mount silicon Zener diodes |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TZA3017HW | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:30 Mbits/s up to 3.2 Gbits/s A-rate fibre optic transmitter |
| TZA3019 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch |
| TZA3019AHT | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch |
| TZA3019AV | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:2.5 Gbits/s dual postamplifier with level detectors and 2 x 2 switch |
| TZA3019AVH | 制造商:未知厂家 制造商全称:未知厂家 功能描述:APPLICATION SPECIFIC AMPLIFIER|DUAL|LLCC|32PIN|PLASTIC |
发布紧急采购，3分钟左右您将得到回复。