- 您现在的位置：买卖IC网 > PDF目录297644 > UPSD3253B-40T6 (STMICROELECTRONICS) 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP52 PDF资料下载
参数资料
| 型号： | UPSD3253B-40T6 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP52 |
| 封装： | PLASTIC, TQFP-52 |
| 文件页数： | 158/189页 |
| 文件大小： | 1638K |
| 代理商： | UPSD3253B-40T6 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页当前第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页第189页
Obsolete
Product(s)
- Obsolete
Product(s)
Standard serial interface (UART)
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
Figure 26 shows a simplified functional diagram of the serial port in Mode 0, and associated
timing.
Transmission is initiated by any instruction that uses SBUF as a destination register. The
“WRITE to SBUF” signal at S6P2 also loads a '1' into the 9th position of the transmit shift
register and tells the TX Control block to commence a transmission. The internal timing is
such that one full machine cycle will elapse between “WRITE to SBUF” and activation of
SEND.
SEND enables the output of the shift register to the alternate out-put function line of RxD
and also enable SHIFT CLOCK to the alternate output function line of TxD. SHIFT CLOCK
is low during S3, S4, and S5 of every machine cycle, and high during S6, S1, and S2. At
S6P2 of every machine cycle in which SEND is active, the contents of the transmit shift are
shifted to the right one position.
As data bits shift out to the right, zeros come in from the left. When the MSB of the data byte
is at the output position of the shift register, then the '1' that was initially loaded into the 9th
position, is just to the left of the MSB, and all positions to the left of that contain zeros. This
condition flags the TX Control block to do one last shift and then deactivate SEND and set
T1. Both of these actions occur at S1P1. Both of these actions occur at S1P1 of the 10th
machine cycle after “WRITE to SBUF.”
Reception is initiated by the condition REN = 1 and R1 = 0. At S6P2 of the next machine
cycle, the RX Control unit writes the bits 11111110 to the receive shift register, and in the
next clock phase activates RECEIVE.
RECEIVE enables SHIFT CLOCK to the alternate output function line of TxD. SHIFT
CLOCK makes transitions at S3P1 and S6P1 of every machine cycle in which RECEIVE is
active, the contents of the receive shift register are shifted to the left one position. The value
that comes in from the right is the value that was sampled at the RxD pin at S5P2 of the
same machine cycle.
As data bits come in from the right, '1s' shift out to the left. When the '0' that was initially
loaded into the right-most position arrives at the left-most position in the shift register, it flags
the RX Control block to do one last shift and load SBUF. At S1P1 of the 10th machine cycle
after the WRITE to SCON that cleared RI, RECEIVE is cleared as RI is set.
12.2.5
More about Mode 1
Ten bits are transmitted (through TxD), or received (through RxD): a start Bit (0), 8 data bits
(LSB first). and a Stop bit (1). On receive, the Stop bit goes into RB8 in SCON. In the
UPSD325xx devices the baud rate is determined by the Timer 1 or Timer 2 overflow rate.
Figure 28 shows a simplified functional diagram of the serial port in Mode 1, and associated
timings for transmit receive.
Transmission is initiated by any instruction that uses SBUF as a destination register. The
“WRITE to SBUF” signal also loads a '1' into the 9th bit position of the transmit shift register
and flags the TX Control unit that a transmission is requested. Transmission actually
commences at S1P1 of the machine cycle following the next rollover in the divide-by-16
counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the
“WRITE to SBUF” signal.)
The transmission begins with activation of SEND which puts the start bit at TxD. One bit
time later, DATA is activated, which enables the output bit of the transmit shift register to
TxD. The first shift pulse occurs one bit time after that.
相关PDF资料 |
PDF描述 |
|---|---|
| UPSD3334D-40U6 | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP80 |
| US1001FL | 0.5 A, 100 V, SILICON, SIGNAL DIODE |
| US1A-HE3 | 1 A, 50 V, SILICON, SIGNAL DIODE, DO-214AC |
| US1B-HE3 | 1 A, 100 V, SILICON, SIGNAL DIODE, DO-214AC |
| US1G-HE3 | 1 A, 400 V, SILICON, SIGNAL DIODE, DO-214AC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| UPSD3253B-40T6T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3253B-40U1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3253B-40U1T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3253B-40U6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3253B-40U6T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
发布紧急采购，3分钟左右您将得到回复。