Obsolete
Product(s)
- Obsolete
Product(s)
Memory blocks
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
1.
Bit Definitions:
Sec<i>_Prot
1 = Primary Flash memory or secondary Flash memory Sector <i> is write-protected.
Sec<i>_Prot
0 = Primary Flash memory or secondary Flash memory Sector <i> is not write-protected.
1.
Bit Definitions:
Sec<i>_Prot
1 = Secondary Flash memory Sector <i> is write-protected.
Sec<i>_Prot
0 = Secondary Flash memory Sector <i> is not write-protected.
Security_Bit
0 = Security Bit in device has not been set; 1 = Security Bit in device has been set.
22.8.2
Reset Flash
The Reset Flash instruction consists of one WRITE cycle (see
Table 85). It can also be
optionally preceded by the standard two WRITE decoding cycles (writing AAh to 555h and
55h to AAAh). It must be executed after:
●
Reading the Flash Protection Status or Flash ID
●
An Error condition has occurred (and the device has set the Error Flag bit (DQ5) to '1'
during a Flash memory Program or Erase cycle.
The Reset Flash instruction puts the Flash memory back into normal READ mode. If an
Error condition has occurred (and the device has set the Error Flag bit (DQ5) to '1' the Flash
memory is put back into normal READ mode within 25s of the Reset Flash instruction
having been issued. The Reset Flash instruction is ignored when it is issued during a
Program or Bulk Erase cycle of the Flash memory. The Reset Flash instruction aborts any
on-going Sector Erase cycle, and returns the Flash memory to the normal READ mode
within 25s.
22.8.3
Reset (RESET) signal
A pulse on Reset (RESET) aborts any cycle that is in progress, and resets the Flash
memory to the READ mode. When the reset occurs during a Program or Erase cycle, the
Flash memory takes up to 25
μs to return to the READ mode. It is recommended that the
for the MCU to retreive the bootstrap instructions after the reset cycle is complete.
22.9
SRAM
The SRAM is enabled when SRAM Select (RS0) from the DPLD is High. SRAM Select
(RS0) can contain up to two product terms, allowing flexible memory mapping.
Table 87.
Sector protection/security bit definition – Flash protection register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sec7_Prot
Sec6_Prot
Sec5_Prot
Sec4_Prot
Sec3_Prot
Sec2_Prot
Sec1_Prot
Sec0_Prot
Table 88.
Sector protection/security bit definition – secondary Flash protection
register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Security_B
it
Not used
Sec3_Prot
Sec2_Prot
Sec1_Prot
Sec0_Prot