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参数资料
| 型号： | UPSD3253B-40T6 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP52 |
| 封装： | PLASTIC, TQFP-52 |
| 文件页数： | 44/189页 |
| 文件大小： | 1638K |
| 代理商： | UPSD3253B-40T6 |
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Obsolete
Product(s)
- Obsolete
Product(s)
I/O ports (PSD module)
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
138/189
24.8
Port configuration registers (PCR)
Each Port has a set of Port Configuration Registers (PCR) used for configuration. The
contents of the registers can be accessed by the MCU through normal READ/WRITE bus
hexadecimal from the base of the CSIOP register.
The pins of a port are individually configurable and each bit in the register controls its
respective pin. For example, Bit 0 in a register refers to Bit 0 of its port. The three Port
Configuration Registers (PCR), shown in Table 96, are used for setting the Port
configurations. The default Power-up state for each register in Table 96 is 00h.
24.8.1
Control register
Any bit reset to '0' in the Control Register sets the corresponding port pin to MCU I/O mode,
and a '1' sets it to Address Out mode. The default mode is MCU I/O. Only Ports A and B
have an associated Control Register.
24.8.2
Direction register
The Direction Register, in conjunction with the output enable (except for Port D), controls the
direction of data flow in the I/O Ports. Any bit set to '1' in the Direction Register causes the
corresponding pin to be an output, and any bit set to '0' causes it to be an input. The default
mode for all port pins is input.
respectively. The direction of data flow for Ports A, B, and C are controlled not only by the
direction register, but also by the output enable product term from the PLD AND Array. If the
output enable product term is not active, the Direction Register has sole control of a given
pin’s direction.
An example of a configuration for a Port with the three least significant bits set to output and
the remainder set to input is shown in Table 99. Since Port D only contains two pins (shown
in Figure 66), the Direction Register for Port D has only two bits active.
24.8.3
Drive Select register
The Drive Select Register configures the pin driver as Open Drain or CMOS for some port
pins, and controls the slew rate for the other port pins. An external pull-up resistor should be
used for pins configured as Open Drain.
A pin can be configured as Open Drain if its corresponding bit in the Drive Select Register is
set to a '1.' The default pin drive is CMOS.
Note:
The slew rate is a measurement of the rise and fall times of an output. A higher slew rate
means a faster output response and may create more electrical noise. A pin operates in a
high slew rate when the corresponding bit in the Drive Register is set to '1.' The default rate
is slow slew.
Table 100 shows the Drive Register for Ports A, B, C, and D. It summarizes which pins can
be configured as Open Drain outputs and which pins the slew rate can be set for.
相关PDF资料 |
PDF描述 |
|---|---|
| UPSD3334D-40U6 | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP80 |
| US1001FL | 0.5 A, 100 V, SILICON, SIGNAL DIODE |
| US1A-HE3 | 1 A, 50 V, SILICON, SIGNAL DIODE, DO-214AC |
| US1B-HE3 | 1 A, 100 V, SILICON, SIGNAL DIODE, DO-214AC |
| US1G-HE3 | 1 A, 400 V, SILICON, SIGNAL DIODE, DO-214AC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| UPSD3253B-40T6T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3253B-40U1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3253B-40U1T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3253B-40U6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3253B-40U6T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
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