Obsolete
Product(s)
- Obsolete
Product(s)
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
Memory blocks
22.5.7
Erase time-out flag (DQ3)
The Erase Time-out Flag bit (DQ3) reflects the time-out period allowed between two
consecutive Sector Erase instructions. The Erase Time-out Flag bit (DQ3) is reset to '0' after
a Sector Erase cycle for a time period of 100s + 20% unless an additional Sector Erase
instruction is decoded. After this time period, or when the additional Sector Erase instruction
is decoded, the Erase Time-out Flag bit (DQ3) is set to ‘1’.
1.
X = Not guaranteed value, can be read either '1' or '0.'
2.
DQ7-DQ0 represent the Data Bus bits, D7-D0.
3.
FS0-FS7 and CSBOOT0-CSBOOT3 are active High.
22.6
Programming Flash memory
Flash memory must be erased prior to being programmed. A byte of Flash memory is
erased to all '1's (FFh), and is programmed by setting selected bits to '0'. The MCU may
erase Flash memory all at once or by-sector, but not byte-by-byte. However, the MCU may
program Flash memory byte-by-byte.
The primary and secondary Flash memories require the MCU to send an instruction to
program a byte or to erase sectors (see
Table 85).
Once the MCU issues a Flash memory Program or Erase instruction, it must check for the
status bits for completion. The embedded algorithms that are invoked support several
means to provide status to the MCU. Status may be checked using any of three methods:
Data Polling, Data Toggle, or Ready/Busy (PC3).
22.6.1
Data Polling
Polling on the Data Polling Flag bit (DQ7) is a method of checking whether a Program or
Erase cycle is in progress or has completed.
Figure 51 shows the Data Polling algorithm.
When the MCU issues a Program instruction, the embedded algorithm begins. The MCU
then reads the location of the byte to be programmed in Flash memory to check status. The
Data Polling Flag bit (DQ7) of this location becomes the complement of b7 of the original
data byte to be programmed. The MCU continues to poll this location, comparing the Data
Polling Flag bit (DQ7) and monitoring the Error Flag bit (DQ5). When the Data Polling Flag
bit (DQ7) matches b7 of the original data, and the Error Flag bit (DQ5) remains '0,' the
embedded algorithm is complete. If the Error Flag bit (DQ5) is '1,' the MCU should test the
Data Polling Flag bit (DQ7) again since the Data Polling Flag bit (DQ7) may have changed
simultaneously with the Error Flag bit (DQ5) (see
Figure 51).
The Error Flag bit (DQ5) is set if either an internal time-out occurred while the embedded
algorithm attempted to program the byte or if the MCU attempted to program a '1' to a bit
that was not erased (not erased is logic '0').
Table 86.
Status bit
Functional Block
FS0-FS7/
CSBOOT0-
CSBOOT3
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Flash Memory
VIH
Data
Polling
Toggle
Flag
Error
Flag
X
Erase
Time-out
XXX