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参数资料
| 型号： | W25Q64DWZPIP |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | PROM |
| 英文描述： | 256K X 32 SPI BUS SERIAL EEPROM, 7.5 ns, PDSO8 |
| 封装： | 6 X 5 MM, GREEN, WSON-8 |
| 文件页数： | 17/82页 |
| 文件大小： | 914K |
| 代理商： | W25Q64DWZPIP |
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W25Q64DW
- 24 -
10.2.8 Write Disable (04h)
The Write Disable instruction (Figure 7) resets the Write Enable Latch (WEL) bit in the Status Register to
a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into the
DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon
completion of the Write Status Register, Erase/Program Security Registers, Page Program, Quad Page
Program, Sector Erase, Block Erase, Chip Erase and Reset instructions.
/CS
CLK
DI
(IO
0)
DO
(IO
1)
Mode 0
Mode 3
0
1
2
3
4
5
6
7
Mode 0
Mode 3
Instruction (04h)
High Impedance
/CS
CLK
Mode 0
Mode 3
0
1
Mode 0
Mode 3
IO
0
IO
1
IO
2
IO
3
04h
Instruction
Figure 7. Write Disable Instruction for SPI Mode (left) or QPI Mode (right)
10.2.9 Read Status Register-1 (05h) and Read Status Register-2 (35h)
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is
entered by driving /CS low and shifting the instruction code “05h”
for Status Register-1 or “35h” for
Status Register-2 into the DI pin on the rising edge of CLK. The status register bits are then shifted out on
the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure 8. The Status
Register bits are shown in Figure 4a and 4b and include the BUSY, WEL, BP2-BP0, TB, SEC, SRP0,
SRP1, QE, LB3-0, CMP and SUS bits (see Status Register section earlier in this datasheet).
The Read Status Register instruction may be used at any time, even while a Program, Erase or Write
Status Register cycle is in progress. This allows the BUSY status bit to be checked to determine when
the cycle is complete and if the device can accept another instruction. The Status Register can be read
continuously, as shown in Figure 8. The instruction is completed by driving /CS high.
/CS
CLK
DI
(IO
0)
DO
(IO
1)
Mode 0
Mode 3
0
1
2
3
4
5
6
7
Instruction (05h or 35h)
High Impedance
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
Status Register 1 or 2 out
*
= MSB
*
Figure 8a. Read Status Register Instruction (SPI Mode)
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| W25X10AVDIAZ | 128K X 8 FLASH 2.7V PROM, PDIP8 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W25Q64FVDAIG | 制造商:WINBOND 制造商全称:Winbond 功能描述:3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI |
| W25Q64FVDAIP | 制造商:WINBOND 制造商全称:Winbond 功能描述:3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI |
| W25Q64FVSFIG | 功能描述:IC SPI FLASH 64MBIT 16SOIC RoHS:是 类别:集成电路 (IC) >> 存储器 系列:SpiFlash® 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:4.5M（256K x 18） 速度:133MHz 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x20） 包装:托盘 |
| W25Q64FVSFIG TR | 制造商:Winbond Electronics Corp 功能描述: 制造商:Winbond Electronics Corp 功能描述:IC FLASH 64MBIT 104MHZ 16SOIC |
| W25Q64FVSFIP | 制造商:WINBOND 制造商全称:Winbond 功能描述:3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI |
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