参数资料
型号: W25Q80BVSSIG
厂商: Winbond Electronics
文件页数: 51/75页
文件大小: 0K
描述: IC FLASH 8MBIT 8SOIC
标准包装: 90
系列: SpiFlash®
格式 - 存储器: 闪存
存储器类型: FLASH
存储容量: 8M(1M x 8)
速度: 104MHz
接口: SPI 串行
电源电压: 2.7 V ~ 3.6 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.209",5.30mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
其它名称: Q4816329
T1015683
W25Q80BV
6.2.32
Read Manufacturer / Device ID Dual I/O (92h)
The Manufacturer / Device ID Dual I/O instruction is an alternative to the Read Manufacturer/Device ID
instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 2x
speed.
The Read Manufacturer / Device ID Dual I/O instruction is similar to the Fast Read Dual I/O instruction.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “9 2 h” followed by a
24-bit address (A23-A0) of 000000h, 8-bit Continuous Read Mode Bits, with the capability to input the
Address bits two bits per clock. After which, the Manufacturer ID for Winbond (EFh) and the Device ID
are shifted out 2 bits per clock on the falling edge of CLK with most significant bits (MSB) first as shown in
figure 30. The Device ID values for the W25Q80BV is listed in Manufacturer and Device Identification
table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by
the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to
the other. The instruction is completed by driving /CS high.
/CS
Mode 3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
Mode 0
Instruction (92h)
A23-16
A15-8
A7-0 (00h)
M7-0
DI
(IO 0 )
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
DO
(IO 1 )
* = MSB
High Impedance
7
*
5
3
1
7
*
5
3
1
7
*
5
3
1
7
*
5
3
1
/CS
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Mode 3
CLK
IOs switch from
Input to Output
Mode 0
DI
(IO 0 )
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
DO
(IO 1 )
1
7
*
5 3
MFR ID
1
7
*
5 3
Device ID
1
7
*
5 3
MFR ID
(repeat)
1
7
*
5 3
Device ID
(repeat)
1
Figure 30. Read Manufacturer / Device ID Dual I/O Diagram
Note:
The “Continuous Read Mode” bits M 7-0 must be set to Fxh to be compatible with Fast Read Dual I/O instruction.
Publication Release Date: October 09, 2013
- 51 -
Revision I
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