参数资料
型号: WJLXT971ALE.A4SE000
厂商: CORTINA SYSTEMS INC
元件分类: 网络接口
英文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP64
封装: LEAD FREE, LQFP-64
文件页数: 85/116页
文件大小: 1172K
代理商: WJLXT971ALE.A4SE000
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
70
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
Figure 40. Power-Up Timing
Table 39. Power-Up Timing Parameters
Parameter
Symbol
Min
Typ1
Max
Units
Test Conditions
Voltage threshold
v1
2.9
V
Power Up delay2
t1
300
s–
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production
testing.
2. Power-up delay is specified as a maximum value because it refers to the PHY guaranteed performance -
the PHY comes out of reset after a delay of No MORE Than 300
s. System designers should consider this
as a minimum value - After threshold v1 is reached, the MAC should delay No LESS Than 300
s before
accessing the MDIO port.
Figure 41. RESET Pulse Width and Recovery Timing
Table 40. RESET Pulse Width and Recovery Timing Parameters
Parameter
Symbol
Min
Typ1
Max
Units
Test Conditions
RESET pulse width
t1
10
ns
RESET recovery delay2
t2
300
s–
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production
testing.
2. Reset Recovery Delay is specified as a maximum value because it refers to the PHY guaranteed
performance - the PHY comes out of reset after a delay of No MORE Than 300
s. System designers
should consider this as a minimum value - After de-asserting RESET*, the MAC should delay No LESS
Than 300
s before accessing the MDIO port.
t1
VCC
MDIO,etc
v1
t2
RESET
MDIO,etc
t1
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