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参数资料
型号： WJLXT971ALE.A4SE000
厂商： CORTINA SYSTEMS INC
元件分类： 网络接口
英文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP64
封装： LEAD FREE, LQFP-64
文件页数： 95/116页
文件大小： 1172K
代理商： WJLXT971ALE.A4SE000
LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
8
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
Revision History
Revision 002
Revision Date: August 6, 2002
Page
Description
Globally replaced “pseudo-PECL” with Low-Voltage PECL”, except when identified with 5 V.
1
Front Page: Changed “pseudo-ECL (PECL)” to “Low Voltage PECL (LVPECL).
Added “JTAG Boundary Scan” to Product Features on front page.
12
Modified Figure 2 “LXT971A 64-Ball PBGA Assignments” (replaced TEST1 and TEST0 with GND).
13
Modified Figure 3 “LXT971A 64-Pin LQFP Assignments” (replaced TEST1 and TEST0 with GND).
14
Modified Table 1 “LQFP Numeric Pin List” (replaced TEST1 and TEST0 with GND).
16
Added note under Section 2.0, “Signal Descriptions”: “Intel recommends that all inputs and multi-
function pins be tied to the inactive states and all outputs be left floating, if unused.”
17
Modified SD/TP description in Table 3 “LXT971A Network Interface Signal Descriptions”.
Added Table note 2.
18
Modified Table 4 “LXT971A Miscellaneous Signal Descriptions”.
19
Modified Table 5 “LXT971A Power Supply Signal Descriptions”.
20
Added Table 8 “LXT971A Pin Types and Modes”.
22
Replaced second paragraph under Section 3.2.1.2, “Fiber Interface”.
23
Added Section 3.2.2.1, “Increased MII Drive Strength”.
23
Changed “Far-End Fault” title to ‘100BASE-FX Far-End Fault”.
Modified first sentence under this heading.
30
Modified Figure 8 “Hardware Configuration Settings”.
35
Added paragraph after bullets under Section 3.6.7.2, “Test Loopback”.
43
Modified text under Section 3.7.3.4, “Fiber PMD Sublayer”.
47
Modified Table 13 “Supported JTAG Instructions”.
47
Modified Table 14 “Device ID Register”.
52
Added a new Section 4.3, “The Fiber Interface”.
53
Replaced Figure 25 “Typical LXT971A-to-3.3 V Fiber Transceiver Interface Circuitry”.
54
Added Figure 26 “Typical LXT971A-to-5 V Fiber Transceiver Interface Circuitry”.
55
Added Figure 27 “ON Semiconductor Triple PECL-to-LVPECL Translator”.
56
Modified Table 17 “Absolute Maximum Ratings”.
56
Modified Table 18 “Operating Conditions”: Added Typ values to Vcc current.
57
Modified Table 20 “Digital I/O Characteristics - MII Pins”.
58
Modified Table 22 “I/O Characteristics - LED/CFG Pins”.
58
Added Table 23 “I/O Characteristics – SD/TP Pin”.
60
Added Table 28 “LXT971A Thermal Characteristics”.
65
Modified Table 33 “10BASE-T Receive Timing Parameters”
72
Modified Table 42 “Register Bit Map”. (Added Table 26 information).
86
Added Table 57 “Digital Config Register (Address 26)”.
87
Modified Table 58 “Transmit Control Register (Address 30)”.
90
Added Section 8.0, “Product Ordering Information”.
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相关代理商/技术参数
参数描述
WJLXT971CA4 制造商:Intel 功能描述:
WJLXT972ALC.A4 功能描述:IC TRANS 3.3V ETHERNET 64-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:25 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:4.5 V ~ 5.5 V 安装类型:通孔 封装/外壳:16-DIP（0.300"，7.62mm） 供应商设备封装:16-PDIP 包装:管件
WJLXT972ALC.A4 S E001 制造商:Intel 功能描述:PHY 1-CH 10Mbps/100Mbps 64-Pin LQFP T/R
WJLXT972ALC.A4-857341 功能描述:TXRX ETH 10/100 SGL PORT 64-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 类型:收发器 驱动器/接收器数:1/1 规程:RS422，RS485 电源电压:4.75 V ~ 5.25 V 安装类型:通孔 封装/外壳:8-DIP（0.300"，7.62mm） 供应商设备封装:8-PDIP 包装:管件 产品目录页面:1402 (CN2011-ZH PDF)
WJLXT972ALC.A4-857345 功能描述:TXRX ETH 10/100 SGL PORT 64-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1 系列:- 类型:线路收发器 驱动器/接收器数:5/3 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC 包装:Digi-Reel® 产品目录页面:918 (CN2011-ZH PDF) 其它名称:296-25096-6
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